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Honored Contributor I
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Arria 10 Dev board sampling LVDS input signals at 1ghz

Hi, 

I'm attempting to input 1 strobe signal (used to start an acquisition window) and 16 data signals into the Arria 10 Development board using the FMC connector. The purpose is to time stamp the 16 data signals with a 1ns resolution which means running the design at 1Ghz, my plan for doing this is having a PLL with two 500mhz outputs 180 degrees out of phase which will clock 2 FIFOs which will have the data going into them. (then read the data out in a slower clock domain) 

I have managed to create a design that passes timing doing this but isn't functioning as desired. I want to know if it is possible to do what I am suggesting?  

 

I don't know if I can use the "Altera GPIO DDIO" IP core or Altera LVDS SERDES to help me make the input pins run at high speeds than a general IO?  

 

Thank you for your help in advance!
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