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Hi all
I was trying to compile my design in quartus 15.0 targeting the Arria 10 fpga device -10AX115R4F40I3SG.I ran just the tcl scripts for pin assignments present in the new Arria 10 EMIF-ddr3 IP generated. Analysis and synthesis ran successfully for the particular device . But it threw error in fitter .The error i got looks like this : 16344 Design requires 11 contiguous fully bonded lanes,but the target device for your design has a maximum of 8 contiguous lanes.Choose a different target device for your design. Did anyone face similar issues before?Link Copied
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Hi Aswathy.p
I just got similar message as yours Design requires 11 contiguous fully bonded lanes, but the target device for your design has a maximum of 24 contiguous lanes. Choose a different target device for your design. From your message, it makes sense if the device has 8 and it requires 11. It is out of range. But, my design requires 11 which is less than the device has. Would mind to share how you did solve this issue? I am using Arria 10 AX066 devices. Thank you- Mark as New
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Can any one answer this? I am facing this same issue. using S10 FPGA. Thanks!
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I am also facing the same issue:
Error(16344): Design requires 7 contiguous fully bonded lanes, but the target device for your design has a maximum of 16 contiguous lanes. Choose a different target device for your design.
This doesn't make any sense.
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