Arria 10 GX FPGA with PCIe core no coreclkout_hip

[TWatt3]

Hello,

I have a board with an Arria 10 GX FPGA on it. 

We are using the PCIe core in the FPGA.

Using SignalTap, we are able to see the PCIe refclk toggle at the expected rate (100 MHz).

We do not see any clock coming out of the PCIe module (coreclkout_hip).

We have used this design on a previous version of the board using a Cyclone V GT FPGA and it worked properly.

I have checked the PCIe transceiver bank voltage and pin connections and they look correct.

I have attached a screenshot of the Qsys design, showing the coreclkout_hip from the PCIe component.

Any ideas what could cause the clock to not be output and how to debug it?

Thanks.

[KhaiChein_Y_Intel]

Hi,

Could you share the signal tap for the below signals? Besides this, could you try running the example design?

serdes_pll_locked

coreclkout_hip

refclk pin

pll_cal_busy

tx_cal_busy

rx_cal_busy

pin_perst

npor

reset_status

pll_locked

rx_is_lockedtoref

rx_is_lockedtodata

ltssmstate[4:0]

lane_act[3:0]

Thanks

Best regards,

KhaiY

[TWatt3]

Hi KhaiY,

I have attached the signaltap waveforms when the board is reset.

Thanks.

Todd Watts

[Lilian_61]

Hi KhaiY,

I want to monitor these signals, but I don't know how to connect then on SignalTap.

I didn't find these output of Hard IP.

Are they the internal signals? How can i connect them correctly and quick to SignalTap.

Could you give some instruction on this?

Thanks

Lilian_61

[KhaiChein_Y_Intel]

Hi,

It looks like the PLL, TX and RX calibration are still in progress. Is the CLKUSR pin clocked from an external free-running clock source and it is available during device power-on?

Thanks

Best regards,

KhaiY

[TWatt3]

Hi KhaiY,

I have the CLKUSR pin tied to ground.  I checked the "Intel Arria 10 GX, GT and SX Device Family Pin Connection Guidlines" document (pcg-01017.pdf and see that the CLKUSR pin must be connected to a clock for the transceivers to work.

So this is probably the problem?

Thanks.

Todd

[TWatt3]

Hi KhaiY,

Is the only option for the CLKUSR clock to drive the CLKUSR pin from an external oscillator for the transceivers?

Is it possible to assign CLKUSR within the FPGA from a 100 MHz clock and not use the external pin?

Thanks.

Todd

[TWatt3]

Hi KhaiY,

Can the calibration clock for the Arria 10 transceivers be re-assigned to a different clock other than CLKUSR?

Thanks.

Todd

[KhaiChein_Y_Intel]

HI,

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance. 

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY

[TWatt3]

Hi KhaiY,

We had the board with the Arria 10 reworked and now have a 100 MHz oscillator connected to the CLKUSR pin.

When we power on the board connected to the PCIe backplane, we see the link come up.

This did not happen before the rework, so the CLKUSR appears to be getting the 100 MHz clock.

We also have a Teradyne Lecroy Summit T24 PCI Express 2.5/5.0 GT/s box to help analyze the PCIe traffic.

On the analyzer, we see it starts at 4 lanes of Gen1 (2.5 Gbps) rate.

Then it tries to switch to Gen2 rate (5 Gbps) and fails.

It reverts to 2 lanes (channels 3 & 2) at Gen1 rate.

We were wondering if we need to do configuration or calibration in the Arria 10 for the transceiver links?

Or is there something else we could look at or try to see why the data is not being accepted?

Thanks.