I have a board with an Arria 10 GX FPGA on it.
We are using the PCIe core in the FPGA.
Using SignalTap, we are able to see the PCIe refclk toggle at the expected rate (100 MHz).
We do not see any clock coming out of the PCIe module (coreclkout_hip).
We have used this design on a previous version of the board using a Cyclone V GT FPGA and it worked properly.
I have checked the PCIe transceiver bank voltage and pin connections and they look correct.
I have attached a screenshot of the Qsys design, showing the coreclkout_hip from the PCIe component.
Any ideas what could cause the clock to not be output and how to debug it?
Could you share the signal tap for the below signals? Besides this, could you try running the example design?
I want to monitor these signals, but I don't know how to connect then on SignalTap.
I didn't find these output of Hard IP.
Are they the internal signals? How can i connect them correctly and quick to SignalTap.
Could you give some instruction on this?
It looks like the PLL, TX and RX calibration are still in progress. Is the CLKUSR pin clocked from an external free-running clock source and it is available during device power-on?
I have the CLKUSR pin tied to ground. I checked the "Intel Arria 10 GX, GT and SX Device Family Pin Connection Guidlines" document (pcg-01017.pdf and see that the CLKUSR pin must be connected to a clock for the transceivers to work.
So this is probably the problem?
The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance.
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We had the board with the Arria 10 reworked and now have a 100 MHz oscillator connected to the CLKUSR pin.
When we power on the board connected to the PCIe backplane, we see the link come up.
This did not happen before the rework, so the CLKUSR appears to be getting the 100 MHz clock.
We also have a Teradyne Lecroy Summit T24 PCI Express 2.5/5.0 GT/s box to help analyze the PCIe traffic.
On the analyzer, we see it starts at 4 lanes of Gen1 (2.5 Gbps) rate.
Then it tries to switch to Gen2 rate (5 Gbps) and fails.
It reverts to 2 lanes (channels 3 & 2) at Gen1 rate.
We were wondering if we need to do configuration or calibration in the Arria 10 for the transceiver links?
Or is there something else we could look at or try to see why the data is not being accepted?