Hello,I am seeing something that I cannot understand from the transceiver user guide. Arria 10GX with 12 tranceiver channels. Of the 12 XCVR channels, I have one x4 PCIe Gen 3 HARD IP and 4 lanes of XAUI. Here is the interesting part - When I instantiate XAUI without the PCIe, the core is able to recover the clock from the rx data stream. But when I instantiate PCIe core, the XAUI core is not able to recover the clock unless the board is plugged into the PCIe slot. Why is this? Thank you for any insights. Best regards, Sanjay
Also, does CLKUSR play a part in this? I have the CLKUSR at 100MHz coming into the device. So I am not sure why PCIe should get in the way of XAUI lanes. PCIe has its own reference clock and XAUI interface it's own. What's interesting is that my colleague here has the exact same issue with the PCIe and JESD204B. It seems like there is something in the PCIe core that we do not understand.
I see this is an old thread - but for what it's worth I just had to deal with same issue (PCIe + DisplayPort). The PCIe hard IP instances (if used) take precedence and actually gate/prevent calibration of any GXBs downstream from them, if the PCIe HIP modules don't calibrate properly (i.e. aren't connected). The cal_busy / cal_done signals are buried in the fabric and can't be manipulated, as far as I can tell. Was looking into faking the calibration complete to bypass situations where PCIe not connected but want to use the rest of the system. Haven't figured out how to do that yet.
See info on page 582 (Sec 7.3 - Power-up Calibration) :