Arria 10 HPS EMIF DDR4 16-bits "Fitter was unable to place an EMIF/PHYLite system"

[Rob49]

Hi.

I'm working on a custom board using a Soc FPGA Arria 10 (10AS048E4F29E3SG) with DDR4 memory (using two components MT40A512M16(TB)062E) linked to the HPS module.

Because of a yet unexplained error, the dq3 lane used to communicate with one of these components fails its calibration on the prototype. As I don't actually needs that much memory for the current state of the project, I've been trying to compile a limited version that will use only one of the memory component (so using a 16-bits wide memory instead of 32-bits).

My problem is that trying to compile the project fails (see error below) when trying to use only 16bits, but I have no compilation error when using the initially expected 32bits.

I have manage to reproduce the problem using a stand-alone quartus project containing only the HPS_EMIF IP, but I don't have the same issue using the FPGA_EMIF IP : see the two linked archives.

Can you help me identify the source of the problem, please ? Thank you in advance.

Rob

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DQ_GRP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic DQ_GRP that is part of Generic Component hps_ddr4_hps_emif in region (78, 87) to (78, 98), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The DQ_GRP name(s): u0|hps_emif|hps_emif|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst_DQ_GRP_1
Error(16234): No legal location could be found out of 3 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: DQ_X9 (2 locations affected)
Info(175029): DQ_GRP containing Y21
Info(175029): DQ_GRP containing Y21
Error(175005): Could not find a location with: HPS_X16 (1 location affected)
Info(175029): DQ_GRP containing Y21
Info(175015): The I/O pad hps_mem_dqs[0] is constrained to the location PIN_AA17 due to: User Location Constraints (PIN_AA17)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within this DQ_GRP

[JingyangTeh]

Hi Rob49

Noted on your case.

I will be investigating the archive attached and will get back to you as soon as possible.

Regards

Jingyang, Teh

[JingyangTeh]

Hi Rob

In the case for the HPS EMIF. In normal use case, the HPS IP core and HPS EMIF IP are usually connected together automatically and we do not need to implement additional constraints.

If we were to make changes to the pin out there are some conditions that to be followed.

Refer to section 3.7.1 in the document below:

https://www.intel.com/programmable/technical-pdfs/683106.pdf

Regards

Jingyang, Teh

[Rob49]

Hi Jingyang.

Thank you for your quick response. This is not what I was hoping to read, but it fits with my situation.

Regards,

Rob

[JingyangTeh]

Hi Rob49

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.

If you happened to close this thread you might receive a survey.  If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh