Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19206 Discussions

Arria 10 IOPLL not locking

mke
Beginner
325 Views

Hello,

 

I have a problem with our Arria 10 based board: the IOPLLs are not locking. None of the IOPLLs work as expected, whatever we do.

 

The exact FPGA model we use is 10AX027E2F29E1HG. And in addition, we have Arria 10 SoC development kit to test with.

 

We have several clocks connected to the FPGA on our board, all banks except 1C and 1D, single-ended clocks, and differential ones, and some very low jitter clocks as well. But none of the clock inputs work as expected, IOPLL just does not lock, the output frequency is totally off and there is awful jitter in the PLL output. We have a very small test setup, there is no logic involved anymore, just clock input, PLL and we connect the PLL output clock to the output pin for measurement. Also, we connect the input clock signal, the one connected to the PLL input, to another output pin and we can see that the frequency is correct and the signal is fine, 100MHz, for example. But the PLL does not lock despite the frequency we set up as the required output clock and the output is sometimes doubled, sometimes triple of what was required.

 

One additional test we did: we connected the internal oscillator to the IOPLL input. This one did not work either but was running fine on the SoC development kit we have.

 

Voltages seem to be correct on our board, with no significant noise either on power rails. And we have tuned the power sequence and even replaced the FPGA on our board once. Nothing helps.

 

One thing I noticed in our design compared to the SoC dev. kit: we have pins C28 (RREF_TL) and AH25 (RREF_BL) unconnected as we do not use the transceivers on banks 1D and 1C. But there is a statement about IOPLLs and these pins in "pin connection guidelines". Are these pins and 2K resistors needed for any IOPLL or just for PLLs located in banks 1D and 1C?

 

Thanks,

Madis

0 Kudos
1 Solution
Ash_R_Intel
Employee
295 Views

Hi,

Pasting here the content of PCG related to RREF pins:

RREF_[T,B][L,R]InputReference resistor for fPLL, IOPLL, and transceiver, specific to the top (T) side or bottom (B) side and left (L) side or right (R) side of the device.If any REFCLK pin or transceiver channel on one side (left or right) of the device or IOPLL is used, you must connect each RREF pin on that side of the device to its own individual 2kΩ resistor to GND. Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

The description says that even if IOPLL is used, you should connect these pins to GND via 2K resistor.

Also suggest you to check the recommendations provided for VCCA_PLL in PCG.


Regards


View solution in original post

2 Replies
Ash_R_Intel
Employee
296 Views

Hi,

Pasting here the content of PCG related to RREF pins:

RREF_[T,B][L,R]InputReference resistor for fPLL, IOPLL, and transceiver, specific to the top (T) side or bottom (B) side and left (L) side or right (R) side of the device.If any REFCLK pin or transceiver channel on one side (left or right) of the device or IOPLL is used, you must connect each RREF pin on that side of the device to its own individual 2kΩ resistor to GND. Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

The description says that even if IOPLL is used, you should connect these pins to GND via 2K resistor.

Also suggest you to check the recommendations provided for VCCA_PLL in PCG.


Regards


mke
Beginner
286 Views

Adding these two resistors did the trick, thanks. PLLs are fine and locking now.

BR, Madis

Reply