the receive status register is showing that the DLL FIFO is empty. The receive PMA is locked to data on all lanes. The only issue being reported is the DLL FIFO being empty. The clocks are correct on both the link side and the reference clock.
I am assuming the DLL FIFO has some clock multiplexer that isn't being set correctly, or something is disabled between the PMA and PCS, or somehow the comma detection circuit is disconnected from the JESD core.
There is no description of a DLL FIFO, and there is no diagram.
What are all the possible sources of why the DLL FIFO would be empty?