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Arria 10 Low Latency 40G Ethernet Fails to compile with VHDL

civey0207
Beginner
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Hello, 

 

I'm trying to evaluate the Low Latency 40G Ethernet core in a VHDL based design. The settings of the core are the same as the example design. I've instantiated the ATX PLL that comes with the core upon HDL generation via the QSYS parameter editor. There are no other blocks in the design, the intent is to take this wrapper and instantiate in a test bench for simulation. 

 

The following error occurs when trying to run synthesis: Error: REFCLK port on the PLL is not properly connected on instance MAC_40G:U1|alt_aeu_40_top:alt_eth_ultra_40_0|alt_aeu_40_eth_2:e40_inst|alt_aeu_40_pcs_assembly:phy.phy_inst|e40_tx_pll_322:TX_PLL_322.txp|MAC_40G_altera_iopll_221_p5aicna:e40_tx_pll_322|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst. This refclk port on the PLL must be connected.
Info: Must be connected

 

When I generate the core in a verilog based design, this error does not occur and the design is able to complete synthesis. As far as I can tell, regardless of whether you pick VHDL or Verilog file outputs in the parameter editor the core is a collection of Verilog files and Quartus creates a VHDL wrapper if VHDL is the file output choice.

 

It seems like there may be a bug in Quartus where a parameter or connection between the VHDL wrapper and the instantiated entities isn't being done correctly and the core fails to synthesize. 

 

I'm using Quartus 22.1 Std Build 915, targeting the Arria 10 10AX115S1F45I1SG, and running on Windows 10. Any advice would be appreciated, the work around for now is to use the Verilog version of the core. 

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ZiYing_Intel
Employee
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Hi civey0207,


I think you see the error in synthesis stage might due to the IOPLL instance in Intel Arria 10 design is not connected to a valid REFCLK signal.


Best regards,

Zi Ying


View solution in original post

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5 Replies
ZiYing_Intel
Employee
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Hi civey0207,


Thanks for submitting the issue.

Please do allow me have some time to look into the issue.


Best regards,

Zi Ying


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ZiYing_Intel
Employee
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Hi civey0207,


Can share your .qar file here? So that I can try debug the issue from my side.


Best regards,

Zi Ying


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ZiYing_Intel
Employee
412 Views

Hi civey0207,


I think you see the error in synthesis stage might due to the IOPLL instance in Intel Arria 10 design is not connected to a valid REFCLK signal.


Best regards,

Zi Ying


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civey0207
Beginner
372 Views

Hello Zi, 

 

Thanks for taking a look at this. I agree with you that the REFCLK is not connected to the IO PLL. However, the IO PLL is instantiated and connected by the Platform Designer Generated HDL as part of the 40G MAC core. The only other external entity I am hooking up to the core is the ATX PLL for the transceiver TX Serial Clock. Below is a picture of the design I am trying to evaluate, it is essentially what is shown in Figure 7 of the Low Latency 40Gbps Ethernet IP User Guide (Doc #683745). And again I will emphasize, this error only occurs when I select VHDL as the Generated HDL output from platform designer. The Verilog Generated HDL does not have this problem. Attached is the .QAR file if you would like to open it and compile.

Thanks, 

 

Chris

 

civey0207_0-1681310354515.png

 

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ZiYing_Intel
Employee
383 Views

Hi civey0207,


Since no hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.


Best regards,

Zi Ying


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