Hello,
I'm trying to evaluate the Low Latency 40G Ethernet core in a VHDL based design. The settings of the core are the same as the example design. I've instantiated the ATX PLL that comes with the core upon HDL generation via the QSYS parameter editor. There are no other blocks in the design, the intent is to take this wrapper and instantiate in a test bench for simulation.
The following error occurs when trying to run synthesis: Error: REFCLK port on the PLL is not properly connected on instance MAC_40G:U1|alt_aeu_40_top:alt_eth_ultra_40_0|alt_aeu_40_eth_2:e40_inst|alt_aeu_40_pcs_assembly:phy.phy_inst|e40_tx_pll_322:TX_PLL_322.txp|MAC_40G_altera_iopll_221_p5aicna:e40_tx_pll_322|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst. This refclk port on the PLL must be connected.
Info: Must be connected
When I generate the core in a verilog based design, this error does not occur and the design is able to complete synthesis. As far as I can tell, regardless of whether you pick VHDL or Verilog file outputs in the parameter editor the core is a collection of Verilog files and Quartus creates a VHDL wrapper if VHDL is the file output choice.
It seems like there may be a bug in Quartus where a parameter or connection between the VHDL wrapper and the instantiated entities isn't being done correctly and the core fails to synthesize.
I'm using Quartus 22.1 Std Build 915, targeting the Arria 10 10AX115S1F45I1SG, and running on Windows 10. Any advice would be appreciated, the work around for now is to use the Verilog version of the core.
