Arria 10 Native Phy Settings

[iiwan]

I am new to Arria 10. When I configured TX PMA, did not find TX PLL clock frequently to choose, as It was in Stratix V. So Arria 10
uses RxRefClk for TX PLL? Or how have I to configure? My clk is same for tx and rx.
And second question, in Stratix V I used 8b/10b codec, word aligner and byte ser/des x2, and had to use byte ordering. So in Arria 10 I did not find byte ordering settings neither in platform designer nor in documentation. I have to implement it by myself, or this functionality inserted in word aligner?

[CheePin_C_Intel · Accepted solution]

Hi,

As I understand it, you have some inquiries related to A10 XCVR instantiation. Please see my responses as following:

1. In Arria 10, the TX PLL ie ATX PLL is instantiated separately and connect to Native PHY

2. User would need to build own byte ordering block in core logic. Sorry for the inconvenience.

Please let me know if there is any concern. Thank you.

[iiwan]

I did not find tx_pll_refclk in pins from Native Phy, or it is only available for connecting in platform designer, where I can connect several modules together? And what about CMU TX PLL?

[CheePin_C_Intel]

Hi,

For your information, I have sent you an email from Forum with an example design for A10 Native PHY. You may refer to the design on the interconnects between modules. Please let me know if there is any concern. Thank you.

[iiwan]

Thanks a lot for your help.

[APPU_appu]

Can you send me the same design to me also

[iiwan]

Write your email address and I send you

[APPU_appu]

Hi @iiwan 

Thanks for the reply 

Here is my mail ID : ashwini@graniteriverlabs.in

Regards 

Ashwini

[CheePin_C_Intel]

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.