Just would like to check with you if you specific inquiry is related to the confusing clkout and coreclkin frequencies as in the A10 user guide Figure 55. If yes, sorry for the inconvenience. For your information, the clkout/coreclkin frequency should be the same and the calculation would be data rate/PCS-PMA interface. There seems to be a bug with the diagram which incorrectly show different frequency. Sorry for the confusion.
Thanks for your update. I will file a case for Factory to look into fixing it whenever there is a update cycle for the user guide. For legacy devices, it might take some time. Sorry for the inconvenience.
Sorry for any confusion. I would like to further elaborate on the right clock frequencies for the 10GBaseR application. The tx/rx_corelkin frequency should be 156.25MHz for XGMII. Whereas the tx/rx_clkout would be data rate/PCS-PMA interface which is 257.8125MHz. Note that tx/rx_clkout are not directly connected to tx/rx_coreclkin. The current Figure 55 seems to be confusing. I will feedback to Factory on the confusion and will request them to update the Figure to reflect the correct connection. Sorry for the inconvenience.
The tx/rx_corelkin frequency should be 156.25Mhz for XGMII. Whereas the tx/rx_clkout would be data rate/PCS-PMA interface which is 257.8125Mhz. OK,This is very reasonable. Could you tell me how frequencies about fifo write and read interface ? it is 156.25Mhz ? if yes, How do 156.25 Mhz and 257.8125Mhz cross clock regions?
For your information, I have managed to have discussion with peers and search into internal database. As I understand it, the FIFO is able to handle data cross clock domain. This is why we are seeing the read and write side clocks are of different frequencies. However, the existing figure note of compensation mode for the FIFO seems to be confusing. I have filed a case to Factory to look into the confusing note and update the note and figure to avoid future customer confusion. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
Will PHY work stably if I clock (in 10gbase-r configuration) tx/rxcoreclkin port with:
1. tx_pma_div_clkout with division factor 33?
2. generated clk 156.25 MHz by IOPLL?
3. generated clk 156.25 MHz by IOPLL with reference like Native PHY?