I am using PCI-E example design for Arria 10.
From the signal tap I could see serdes_pll_locked is high and tx_st_ready is high.
But rx_signaldetect is low.
I have assigned the Perstn input to the top level design high.Please help me understand what is going wrong.I am not sure whether PCI-E is enable d on the host side.
Hi, probably you can use this checklist: https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005RVNQA2&action=view&language=en_US
Usually it is related to the setting from host side because no response from the host side.
Since you are using the common clock from mother block, you need to enter the BIOS and set the PCIe slot correctly.