We have two PCB designs with Arria 10 FPGAs on then and in both designs we are able to program the devices using the byte blaster 2 cable over JTAG, but on both boards programming over passive serial fails after sending 240000 bytes. We see this problem with our own configuration firmware and using the byte blaster 2 cable with Quartus prime. We have triple checked the design and layout and we have confirmed the clk and DATA0 have the correct RBF data at the start, so there are no spurious bits etc. MSEL bits are set to 1 per the a10 config guide. The problem happens on multiple boards so it isn't likely a bad chip/manufacturing problem.
We are out of ideas, so any suggestions on things to look up gratefully accepted..
Just would like to check with you, with passive serial configuration scheme, you need a HOST such as CPLD or any microprocessor for the configuration. Is it connected properly?
You may take a look at the user guide below:
It turns out the hardware designer had connected to the AS_DATA0 pin and not the Altera_DATA0 pin. In order to use the 20 prototypes with this mistake, the only option is to implement programming over JTAG from our onboard microcontroller. Since this mechanism doesn't appear to be documented, I'm going to try and reverse engineer the algorithm from the JAM file.
if you have any documentation on this method it would be very helpful ? I can't use the JAM player source code as is since it requires way more memory than our microcontroller has.
The only way is to find out the JTAG pin in your microcontroller as shown in the user guide: