Arria 10 SI Devkit - Support

[MK_ABQ]

Hello,

We are planning to use Intel Arria 10 SI Development Kit for one of our projects. Can you help to answer the following two questions?

Development Kit Link:

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-gx-signal-integrity.html?wapkw=arria%2010%20gx%20fpga%20development%20kit

Q1) In order to test 64 LVDS pairs  as loopback, should we go for any SMA cables?.

Q2) What would we need to test 8 lanes of JESD 204B?

Thanks

[Ash_R_Intel · Accepted solution]

Hi,

The Arria 10 SI dev kit has very limited number of external connectors and no FMC connector as well. So, I think looping back 64 channels at a time will not be possible. Please check the board User Guide section 5 for the details on the available connectors and even transceiver channels.

For JESD204B, you may like to use the JESD204B Intel® FPGA IP and test it on the board by connecting to available XCVR channels. Reference designs are also available on following webpage: https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/jesd204b.html

Regards