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Altera_Forum
Honored Contributor I
1,779 Views

Arria 10 SX - The Fitter cannot place logic IO_LANE ???

Hello, 

 

Actually, I use a Reflex CES Achilles board with a SoC FPGA Arria 10 (10AS066H4F34E3SG). The board is also equipped with two DDR4 memory (2x8 GB). One of them can be accessible from the FPGA. 

 

My first project is a Nios2 with witch I access to the DDR4 memory. The implementation and the Pin Planner were in the ZIP file. 

 

However, when I execute the placement, I get the following error : 

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 

Error (175020): The Fitter cannot place logic IO_LANE that is part of Arria 10 External Memory Interfaces nios2_ddr4_altera_emif_161_oahhcqa in region (148, 6) to (148, 199), to which it is constrained, because there are no valid locations in the region for logic of this type. 

Info (14596): Information about the failing component(s): 

Info (175028): The IO_LANE name(s): nios2_ddr4:inst|nios2_ddr4_altera_emif_161_oahhcqa:ddr4|nios2_ddr4_altera_emif_arch_nf_161_zbuqi6y:arch|nios2_ddr4_altera_emif_arch_nf_161_zbuqi6y_top:arch_inst|altera_emif_arch_nf_io_tiles_wrap:io_tiles_wrap_inst|altera_emif_arch_nf_io_tiles:io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst 

Error (11238): The following 0 locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters. 

Info (175013): The IO_LANE is constrained to the region (148, 6) to (148, 199) due to related logic 

Info (175015): The I/O pad ddr4_alert_n is constrained to the location PIN_AH4 due to: User Location Constraints (PIN_AH4) 

Info (14709): The constrained I/O pad drives a TILE_CTRL, which drives this IO_LANE 

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. 

Error (16297): An error has occurred while trying to initialize the plan stage. 

Error: Quartus Prime Fitter was unsuccessful. 6 errors, 6 warnings 

Error: Peak virtual memory: 2738 megabytes 

Error: Processing ended: Thu Feb 23 12:56:15 2017 

Error: Elapsed time: 00:00:45 

Error: Total CPU time (on all processors): 00:00:44 

Error (293001): Quartus Prime Full Compilation was unsuccessful. 7 errors, 26 warnings 

 

I don't see where the problem lies. Can you help me please ? Thank you very much. 

 

Jo.
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
344 Views

Without looking at your attachment, I'd go back into Qsys and the IP Parameter Editor for the HPS. If there are I/O conflicts, they should be flagged there. You shouldn't have to make changes in the Pin Planner since your choices in the IP Parameter Editor determine which pins to use for the memory interface. Also, if you happen to be using Quartus Prime Pro, try using BluePrint. That might help to isolate what is conflicting.

Altera_Forum
Honored Contributor I
344 Views

Joco, did you ever resolve your problem. I have the same issue. @sstrell, qSys doesn't complain only at compile time do you get this error.

Altera_Forum
Honored Contributor I
344 Views

I use the same Achilles board as joco83. I got the same error when trying to port my design to the board. It may be as sstrell writes that there is an I/O conflict with the HPS I have not looked at the HPS yet. But I noticed that the DDR4 test design from Reflex CES compiles. So I compared assignment from the two project and found some differences. These are the assignments I changes. I do not know which ones are responsible but afterwards the error is gone and the project compiles. Maybe the HPS_EARLY_IO_RELEASE OFF? -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name OPTIMIZATION_MODE BALANCED +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING AUTOMATIC +set_global_assignment -name PROJECT_IP_REGENERATION_POLICY NEVER_REGENERATE_IP +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP OFF +set_global_assignment -name HPS_EARLY_IO_RELEASE OFF +set_global_assignment -name CVP_MODE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF

SYi
Beginner
344 Views

At the ReFLEX's Knowledge base, I found below answer.

 

[FW]-[Achilles]-[Clocks]- I/O conflicts with clocks

Posted by Olivier Thomann on 31 October 2018 05:26 PM

Issue description:

There can be a conflict between both DDR4 and clk_25mhz_fpga clocks in the design. Both inputs try to access the same I/O PLL.

You may have the following error with Quartus Prime Pro:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s)).

 

Resolution advise:

You can add a "Global Clock" constraint on clk_25mhz_fpga, even if it results to a non-optimal PLL placement:

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_25mhz_fpga

 

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