Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Arria 10 Soc DevKit Golden Top will not build

Honored Contributor II

I have an Arria 10 SoC DevKit that I'm using for a project. While studying the platform, I just tried to build the examples/golden_top/PRD/golden_top project that ships with the devkit sw download. 


For some reason, it will not build to completion. Synthesis appears to complete just fine, but planning fails with the following error: 



Critical Warning (18326): The design pin 'CLKUSR' has been assigned to CLKUSR pin location 'AP20'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transcievers and certain IOs. If the pin 'CLKUSR' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'. 

Error (12342): Can't turn on open-drain option for differential I/O pin DP_AUX_CH_N 

Error (12342): Can't turn on open-drain option for differential I/O pin DP_AUX_CH_P 

Error (16297): An error has occurred while trying to initialize the plan stage. 

Error: Quartus Prime Fitter was unsuccessful. 4 errors, 501 warnings 

Error: Peak virtual memory: 3134 megabytes 

Error: Processing ended: Thu Mar 30 10:37:18 2017 

Error: Elapsed time: 00:00:42 

Error: Total CPU time (on all processors): 00:00:42 

Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1782 warnings 



Is this a known problem? Is there a workaround or fix? 


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Honored Contributor II

I tried compiling this before and it works for me without errors... 


I believe this is for Rev C of their board. I used Quartus 16.1 on linux machine to perform compilation.