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Arria 10 TRX re-calibration during JTAG programming

JPrig
Beginner
227 Views

Hi,

I debug a custom Arria 10 design where a receiver CDR does not manage to hold itself locked to data. I see that a stable free-running clock is required at CLKUSR and TX PLL before device power-up/ configuration. I do not think my clocks are stable at device power-up, but they are stable when I manually reconfigure the FPGA through the JTAG. Will a JTAG programming cycle trigger transceiver re-calibration? Or do I have to manually trigger a recalibration because the clocks are not stable at power-up?

Thanks, Julia

 

 

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1 Solution
Ash_R_Intel
Employee
198 Views

Hi Julia,


Please refer this link: https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#lbg14901240...


Pt#2:

The reconfiguration block performs the following steps:

  1. Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core to the requested speed.
    1. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
    2. Selects the corresponding transceiver PLL.
    3. Triggers the transceiver recalibration.


Regards.



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2 Replies
Ash_R_Intel
Employee
199 Views

Hi Julia,


Please refer this link: https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#lbg14901240...


Pt#2:

The reconfiguration block performs the following steps:

  1. Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core to the requested speed.
    1. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
    2. Selects the corresponding transceiver PLL.
    3. Triggers the transceiver recalibration.


Regards.



JPrig
Beginner
180 Views

Hi,

thanks for your reply. This clarified by doubts.

Regards,

Julia

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