Arria 10 Transceiver clock inputs routed to I/O pll(s)

[PJoer2]

Hi,

We would like to know whether it is possible to use a 20 Mhz HCSL clock connected to one of the ARRIA10 **transceiver clock inputs**

as input to I/O plls (not fplls) inside the FPGA.

Testing this with a Quartus design does not show any errors. Within the post-mapping technology map viewer things also look reasonable.

However, what still brings us to ask this question are the following two points:

1)Within timing analysis of the clock path we encounter a signal like the following<input_clk_name>/ch1_pld_pma_fpll_fbclkout_lc_lvpecl_to_coreclk

Since fpll is mentioned we are afraid that the clock passes an fpll which accepts only input frequencies **above 25/30 MHz** and would fail for our 20 MHz clock signal

2)Within ARRIA10 datasheets and reference guides we can not find a clear statement which says something like "a transceiver clock input signal can be routed to the global clock network (and hence to an I/O pll) without having to pass the fpll.

Note: We know that using a dedicated clock input (not transceiver clock input) would solve the problem. However, for our specific application we have other reasons to use the transceiver clock input instead. In addition we are aware that if the above is possible, jitter would be worse.

[CheePin_C_Intel]

Hi,

As I understand it, you are trying to share and connect the XCVR refclk to an IO PLL and you understand that XCVR jitter performance will be impacted. For your information, as per the device datasheet, the minimum frequency validated for XCVR refclk is 25MHz which is for fPLL. Currently, there is no data for supported refclk freqeuncy at 20MHz. Thus, it is difficult to guarantee the functionality of XCVR refclk with 20MHz. You might need to look into using support frequency range. Sorry for the inconvenience.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[PJoer2]

Hi,

many thanks for the prompt answer.

For our reference, can you please point me to the datasheet/page where it is mentioned that

min XCVR refclk is 25 MHz?

For min fpll refclk, I can find 25 MHz in the ARRIA10 datasheet.

For XVCR refclk I can not find a specification...maybe I have tomatos on the eyes :).

Or if there was a statment about XCVR refclk necessarilly going through fpll to reach iopll, this would of course also be sufficient.

Many thanks again and kind regards

Philipp

[CheePin_C_Intel]

Hi, Sorry for any confusion. Yes, you are right. I am referring to TX PLL refclk frequencies ie ATX PLL, CMU PLL and fPLL in the Arria 10 datasheet. I believe it is the same table that you are referring to. The ATX, CMU and fPLL are sourcing their refclk from XCVR refclk pin. In other words, these frequencies are validated supported frequencies for XCVR refclk. Please let me know if there is any concern. Thank you. Best regards, Chee Pin