Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20693 Discussions

Arria 10 cannot access Transceiver ATX PLL reconfiguration interface

LFrin
New Contributor I
852 Views

Hello,

I am currently try to recalibrate the Transceiver ATX PLL on an Arria 10 FPGA (10AX027E4F29E3SG) because the reference clock is not available at FPGA configuration. I use the NIOS V and connect in Qsys the reconfiguration interface with the data manager of the Nios. The NIOS clock which I also use as reconfiguration clock is 100 MHz. The system is not stuck in reset.

 

Qsys ATX PLL reconvQsys ATX PLL reconv

ATX PLL reconv settingsATX PLL reconv settings

After the external clock chip has been successfully configured by the NIOS and the clock is available at the reference clock input of the transceiver, I try to access the reconfiguration interface.

Unfortunately there is nothing but 0x000000FF in the memory area of the NIOS where the reconfiguration interface should be.

 

ATX PLL reconv address in niosATX PLL reconv address in nios

 

The first step of the reconfiguration flow is to write 0x2 to 0x0:

Page 592 Intel® Arria® 10 Transceiver PHY User Guide: Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].

But it does not work. Can someone explain to me where I took a wrong turn? Or is there anything here that I am doing grossly wrong?

 

Some more informations:

Page 586 Intel® Arria® 10 Transceiver PHY User Guide: This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon memory-mapped interface arbitration with PreSICE is enabled or not.

0x280[2] PreSICE Avalon memory-mapped interface control.
0x1: PreSICE is controlling the internal configuration bus.
0x0: The user has control of the internal configuration bus.
0x280[1] ATX PLL pll_cal_busy
0x1: ATX PLL calibration is running
0x0: ATX PLL calibration done

After i write 0x2 to offset address 0x0[7:0] the 0x280[2] stays at PreSICE (0x1) and i dont get the control of the bus.

 

Regards, LFrin

 

0 Kudos
1 Solution
LFrin
New Contributor I
770 Views

Hi,

i found the problem. It is hardware related:

I found it strange that the integrated processor, which takes care of the initial callibration, did not react. If I understand correctly, it is clocked by the 100 MHz user clock (clkusr). I checked the 100 MHz oscillator and well... it does not work. Since we don't use this oscillator for anything else, we didn't notice it earlier.

Thanks for the help, my problem is solved.

 

Regards, LFrin

 

View solution in original post

0 Kudos
6 Replies
Kshitij_Intel
Employee
817 Views

Hi,


Is your design includes an Avalon master that can access the dynamic reconfiguration registers using the Avalon® memory-mapped interface?


Can you please refer Recommendations for Dynamic Reconfiguration for TX PLLs.


https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/recommendations-for-dynamic-reconfiguration.html


Hope this will solve your query.


Thank you

Kshitij Goel


0 Kudos
LFrin
New Contributor I
814 Views

Hi,

 

i try to access the dynamic reconfiguration interface directly from the Nios V. Is that not possible? Do i have to use an bridge?

I do not find any documentation for this topic (using nios and transceiver reconfiguration interface).

 

Thanks for the link, i will read the document again, perhaps i missing something.

 

Regards, LFrin

 

0 Kudos
Kshitij_Intel
Employee
805 Views

Hi,


In all our transceiver example designs with Nios II/NiosV We have used a custom component to access the dynamic reconfiguration interface of the transceivers called reconfig_mgmt_hw.tcl directly. So if you instantiate this in your .qsys system you have direct access to the transceiver configuration interface. I suggest you have a look at the demo designs. For A10 you can find them here :

https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Arria-10-Series/ta-p/735131


Hope this will solve your query.


Thank you

Kshitij Goel


0 Kudos
LFrin
New Contributor I
800 Views

Hi,

I have implemented the component you mentioned, but unfortunately it does not work. I have the same error: The register Bit 0x280[2] stays at 0x1, i do not get the control over the reconfiguration interface... The memory area looks exactly like shown in my first post.

I tried it with Nios II and V there was no difference.

Why can't I get control over the reconfiguration interface? Is it possible that the so-called PreSice is not working properly?

 

Regards, LFrin

0 Kudos
LFrin
New Contributor I
771 Views

Hi,

i found the problem. It is hardware related:

I found it strange that the integrated processor, which takes care of the initial callibration, did not react. If I understand correctly, it is clocked by the 100 MHz user clock (clkusr). I checked the 100 MHz oscillator and well... it does not work. Since we don't use this oscillator for anything else, we didn't notice it earlier.

Thanks for the help, my problem is solved.

 

Regards, LFrin

 

0 Kudos
Kshitij_Intel
Employee
759 Views

Hi,


I’m glad that your problem has been resolved, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel


0 Kudos
Reply