When instantiating an fPLL (in Qsys) with a reference clock frequency of 50 MHz the fitter reports the following error:
Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Error (15744): In atom 'FS2_Arria:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|fpll_inst'
Error (15744): The settings must match one or more of these conditions:
Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode == UNUSED ) OR ( refclk inside {0:49000000,210000000:68719476735} ) OR {((set_fpll_input_freq_range*36'h00002625a0)>((refclk-36'h0002faf080)-36'h00001312d0))}
Error (15744): But the following assignments violate the above conditions:
Error (15744): pll_sup_mode = USER_MODE
Error (15744): prot_mode = BASIC_TX
Error (15744): reference_clock_frequency_scratch = 50000000
The target device is an Arria 10 and I use the fPLL in Core mode, i.e. I don't use it for a transceiver but for synthesizing some user clock.
The error message suggests that I have to change on of the parameters sup_mode, prot_mode or refclk. However
- sup_mode ist not meant to be changed by the user (it is also not accessible from Qsys)
- UNUSED is not a valid value for parameter prot_mode
Which leaves me with changing the refclk frequency. Indeed, if I change to 40 MHz, the fitter does not report any errors.
My question is: is this a real limitation or is there another way avoiding this error? Where does this limitation come from and where is it documented?
Thanks in advance!
