Arria V Avalon-MM Hard IP for PCIe PLL lock

[KSMark]

Is there a pin from the Avalon-MM Arria V Hard IP for PCI Experess that I can monitor the serdes_pll_locked signal or someother downstream signal I can infer the pll lock state.  I am getting an occasional reset from the PCIe core(during and ESD event).  I have mostly ruled out the reset going into the part and would like to determine if my clock is remaining stable.

I am using quartus version 18.1.0 and the part is an 5AGXMB7G4F35I5.

[Farabi]

Hello, 

You can create another pin connected to the serder_pll_locked or coreclkout_hip clock signal with platform designer to monitor the pll locked signal. 

regards,
Farabi

[Farabi]

attached is userguide

[Farabi]

Hello,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,

Farabi