Arria V DDR3 UniPHY Report DDR

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Arria V DDR3 UniPHY Report DDR

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Hi,all,I use QII14.0.2 and my chip is 5AGXMA5D4F27C5.I instantiated two DDR3 SDRAM Controller with UniPHY in Qsys,and the memory clock frequency is 500Mhz.I finish compilation but report DDR timming have some issue(the Address Command Path not passed).How can I solution it?Should I modify the parameter at Board Settings tab?How to do?

thanks for your helps.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9809&stc=1

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