Arria V LVDS IO

[Altera_Forum]

Hello, 

 Knowledge base (http://www.altera.com/support/kdb/solutions/fb128391.html) states: "You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only" That solution also says that Quartus will not issue an error. So, I am trying to figure out which pins they are talking about. How can I tell from the pinout documentation or from Quartus which pins are LVDS I/O standard-enabled?  Thank you for your help!

[Altera_Forum]

Basically, what it is saying is that only dedicated clk pins can be used in LVDS mode. You can see these pins from the pin-planner. 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=7380

[Altera_Forum]

Thanks fpgabuilder! 

What is confusing to me is that those none of the pins on the right side of the device support LVDS - not even the clock input pins. At least this is true for 13.0dp1. I am not using any PLL inputs on that side, but I am using some of those pins as regular I/O. Are you saying that those pins shown as "PLL/DLL related" should only be used for PLL inputs? If that is the case, one of those pins is a DQS (pin T1 in your device), which pretty much makes that DQ group unusable for DDR -- does that sound correct?  Thank you!

[Altera_Forum]

Try Quartus 12.1 sp1. In my design I use these pins to bring in lvds clk input which is provided directly to a pll. But when i tried my design with Quartus 13.0, it failed. It seems they determined that it was a defect in QII 13.0. Reading again through the KB article in your post it seems like Quartus 13.0 will let you use the i/os as LVDS but it may not function correctly!? 

 Yes! I am not sure about the DDR core. It'd be interesting to note.

[Altera_Forum]

You are correct. 12.1 sp1 lets me assign LVDS to the clock input pins on the right side (8 pins total). However, 12.1 sp1 has an incorrect pin layout for the device I am using - that was fixed in 13.0 -- So, my choice is to trust incorrect version number 1 or incorrect version number 2. 

I guess I will file support request and see what they mean. The SR mentions the issue was found in 13.0sp1, which I cannot find.

[Altera_Forum]

I can't find it either. I was told that it would available today. Maybe wait till EoB. But I can feel your pain. As these devices are getting complex, even the 1000 page documentation is not enough to bring out the subtleties that can make or break a design. 

 -sanjay

[Altera_Forum]

I was informed that 13.0 sp1 will be out July 1st.

[Altera_Forum]

I can't wait. It will probably be after the 4th... never waste a holiday to delay a release. :-) 

I think I figured out what knowledge db entry means. I think it means that you can only select the LVDS I/O standard if you intend to use the selected pins for a PLL input. Let's see what sp1 will do.