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Altera_Forum
Honored Contributor I
769 Views

Arria V tranceiver clocking

Hello! 

I need to use all the 24 tranceivers inside the 5AGXFA5H4F35I5 chip. I try to connect them as mentioned in 

AV53002 Figure 2-31: Six Bonded Receiver Channels with Rate Match FIFO Enabled Using Fractional PLL 

 

So I instantiate the fPLLs and Native PHYs with external fPLL, 2 to 6 xN-bonded channels, PCS with rate match FIFO. Channel 0 was placed to physical channel 1 or 4 of each bank. But the compiler always add the common TX clock divider for each bonded group, like this: 

altera_xcvr_native_av:group6_inst|av_xcvr_plls:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_plls.gen_tx_plls.tx_plls|master_cgb.tx_cgb 

 

This divider occupies one additional TX channel, so all the 24 channels does not fit. 

Using 8 fPLLs and x1 clock tree only gives the successfull fit. But really I need 8 channels at 3,125 Gbit/s and 16 channels at 2,5 Gbit/s - which is impossible using groups of 3 tranceivers. 

 

What is wrong? Is there some design example with such tranceiver configuration to start from?
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2 Replies
Altera_Forum
Honored Contributor I
40 Views

This question continues another thread: 

https://www.alteraforum.com/forum/showthread.php?t=37458
Altera_Forum
Honored Contributor I
40 Views

It seems to be soved. Only Quartus ver. 13.1 points me to reset connection. 

[tx_analogreset(0)] must be the same as [~pll_powerdown(0)]. In this case only the comiler merges additional TX clock divider (which is reseted by ~pll_powerdown(0)) with others (which are - tx_analogreset())
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