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Arria10 Embedded Memory

Yamada1
Beginner
292 Views

I have a question about Embedded Memory. I plan to use Arria10's M20K block RAM with 2-Port RAM.

In figures 1 and 4 of the user guide, the input signal to the RAM block transitions at the falling edge of the clock. I could not find a hold time specification for the input of the RAM block, so am I correct in understanding that the timing in the figure is recommended?

We are not familiar with English, so please forgive us for posting machine-translated sentences.

I'm sorry to bother you when you're busy, but it would be helpful if you could teach me.

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ShengN_Intel
Employee
259 Views

Hi,


Check out this document link https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/about-embedded-memory-ip-cores.html (Page 41) onwards, the Design Example may be can help you as well.


Thanks,

Best Regards,

Sheng


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4 Replies
FvM
Valued Contributor III
282 Views

Generally, timing analysis will take care of sufficient hold time. You'll notice that maximal A10 block RAM clock frequency is rather high, e.g. > 500 MHz. Respectively you can expect a low hold time requirement, probably < 1 ns. 

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Yamada1
Beginner
253 Views

Mr. FvM

 

Thank you for your answer.

It was very helpful.

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ShengN_Intel
Employee
260 Views

Hi,


Check out this document link https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/about-embedded-memory-ip-cores.html (Page 41) onwards, the Design Example may be can help you as well.


Thanks,

Best Regards,

Sheng


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Yamada1
Beginner
253 Views

Thank you for your answer.

I checked the documentation.

Even in the simulation waveform, the input to the RAM block was transitioned at the falling edge of the clock, so I recognized this as a recommendation.

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