Arria10 , Error by use Generic Serial Flash controller

[scong5]

Hi

I generate a Generic Serial Flash controller refer to the "Generic Serial Flash Interface Intel FPGA IP Core User Guide" .

It sucessed after Generate HDL . But faild at "Processing ➤ Start ➤ Start Analysis and Elaboration" . It can't find & open some files but I can open these files by notepad. 

I attach my project files , please tell me how should I do .

Thanks

[JohnT_Intel]

Hi,

The reason that you are observing the issue on compiling the design is due to your Quartus project is setting it as Passive Serial. In order to use the "Generic Serial Flash Interface Intel FPGA IP" you will need to change your configuration mode to Active Serial.

You can go to "Assignments --> Device --> Device and Pin Options... --> Configuration --> Configuration Scheme = Active Serial"

or add the below line to "generic_flash_access.qsf"

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"

set_global_assignment -name USE_CONFIGURATION_DEVICE ON

set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ

[scong5]

Hi

I change the  Device and Pin Options to Active Serial x 4 , but the error can't be resolve.

Any other problems ?

[JohnT_Intel]

Hi,

I have tried to compile your latest design but does not observed any error. Could you provide me the detail of the error that you observed?

[scong5]

I run the Quartus Prime Version 18.0.0.219 by Administrator mode.

Processing -> Start -> Start Analysis & Synthesis

Then there are many errors such as :

Error(13225): Can't open VHDL or Verilog HDL file "ip/generic_flash_access/generic_flash_access_intel_generic_serial_flash_interface_top_0/intel_generic_serial_flash_interface_xip_180/synth/generic_flash_access_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_xip_180_tsjvvby.sv" 

Error(13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/generic_flash_access/generic_flash_access_intel_generic_serial_flash_interface_top_0/intel_generic_serial_flash_interface_xip_180/synth/generic_flash_access_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_xip_180_tsjvvby.sv' 

The files exist but the compiler can't find them .

[JohnT_Intel]

Hi,

Could you extract the qar file that you provided to see if you are still seeing the issue?

[scong5]

OK, I still wait for your answer

[JohnT_Intel]

Hi,

Could you try the attach QAR file?

[scong5]

Can't restore

Please check the log file​.

[JohnT_Intel]

Hi,

May I know what is your PWD directory? May I know if you are able to goto a shorter PWD location?

[scong5]

The license file is locate at C:\QuartusLicense .

[JohnT_Intel]

Hi,

What I mean is the location of your project? The reason is that Windows is not able to handle long directory.

[scong5]

The project loation is C:\FPGA2 , please check the report file .

[JohnT_Intel]

Hi,

It looks like the generated file is hitting the path limit. Could you reduce the file name of your project and the IP? Windows only support 256 character for the total path including file name. (https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/fb74100.html)

If you are still facing the issue then I would recommend you to use Linux system.

[scong5]

OK，Pass

Info: Quartus Prime Synthesis was successful. 0 errors, 4 warnings 

Info: Peak virtual memory: 1078 megabytes 

Info: Processing ended: Tue Feb 11 16:29:19 2020 

Info: Elapsed time: 00:01:42 

Info: Total CPU time (on all processors): 00:02:05 

[JohnT_Intel]

Hi,

I am glad to hear that you are able to compile your design now.

[scong5]

OK, Thank your for your support .

[JohnT_Intel]

Glad to help

[JohnT_Intel]

Hi,

The reference design in the user guide is refer to the reference design in Design Store (https://cloud.altera.com/devstore/platform/2179/).