Hi,I am currently migrating a ArriaV board to Arria10. After designing a decoupling scheme with PDN Design Tool 2.0, I had a look on the Arria10 GX DevKit for reference and was a little shocked. On the DevKit there is a huge amount of large bulk capacitors (330µF) and only large decoupling capacitors (4.7µF). No smaller caps... In my PDN-design, most capacitors have less than 1µF (down to 10nF). I know, different designs require different decoupling, but this difference makes me think that I'm doing something wrong. Best regards Martin
Read AN-738 (Arria 10 Device Design Guidelines):https://www.altera.com/en_us/pdfs/literature/an/an738.pdf "Arria 10 devices include embedded on-package and on-die decoupling capacitors to provide high-frequency decoupling. These low-inductance capacitors suppress power noise for excellent power integrity performance, and reduce the number of external PCB decoupling capacitors, saving board space, reducing cost, and greatly simplifying PCB design." The PDN tool should have known this. Did you target the right device with the tool?
I just realized my pdn-Tool was outdated (version 14.0).The download link I used was: https://www.altera.com/content/dam/altera-www/global/en_us/others/literature/ug/pdn_tool_20_a10.zip But I can't remember from what site/document it was linked. The correct one I just downloaded is 16.0: https://www.altera.com/content/dam/altera-www/global/en_us/others/technology/signal/power-distributi... The results of the new one match better the AN-738 phrase... Thanks and best regards Martin