Hi,I am interfacing a SPI slave, which requires chip select to be held low, for the entire duration of transfer. But, looks like chip select is toggled after every byte transfer. Tried workaround of changing the clock phase. It works fine a single register read and register write. But the SPI slave needs to be written a bulk data of 6000 odd bytes in a single stretch(with chip select held low, for the entire duration). What I observe is, the clock phase change is affecting the transfer. When I read back, I am seeing last two LSbs to be 00 in case of 01. I also tried configuring chip select as GPIO and held low, from userspace, but looks like it did not help. Any suggestion to address this issue ? I am using Arria10 based SoC.
Two observation to add to it,1. Along with configuring CS as GPIO, even I had to enable the corresponding CS bit in the SPI HPS register. 2. With CS as GPIO, MOSI, CS and CLK lines are having voltage levels, 0v to 3.3v. But for some reason MISO is having a voltage range of 3.3v to 1.6v. MISO is clamped to 1.6v. So ARM HPS SPI reads back 0xffff When tried with workaround suggestion of changing the Clock phase, MISO is toggling properly between 0v to 3.3v as expeccted. But as mentioned above, with clock phase change, I am having issue with bulk write and bulk read. Anybody has observed similar issue ? Any suggestion ?