Arria10 Transceiver PHY Design Example

[A_MISHRA]

Hi, We are looking for design example for arria 10 transceiver phy test using transceiver toolkit. Our FPGA is 10AS066K2F40E1HG and we are using Quartus Prime Pro 17.1. Design example given on following link is not opening

https://fpgawiki.intel.com/wiki/Arria10_Transceiver_PHY_Basic_Design_Examples#Arria_10_Native_PHY_with_Transceiver_Toolkit_design_example

[CheePin_C_Intel]

Hi,

Sorry for the inconvenience due to the wiki page. For your information, I have emailed you the design ZIP to your email. Please let me know if you are still not receiving it.

Thank you.

[A_MISHRA]

Hello @cheepinc_Intel​ sir,

  Thank you for help. I got the design example through mail, will try it and will get back to you if any further issues are there.

Regards,

Ajay S Mishra

[A_MISHRA]

Hello @cheepinc_Intel​  sir, actually our hardware was having issue. We are using ARRIA 10 FPGA(10AS066K2F40E1HG), and CLKUSR pin should be given with 100-125 MHz clock for transceiver bank calibration. But we have not given this clock , after providing 100 MHz clock to this CLKUSR pin, our transceiver bank started working , so our Arria10 Transceiver PHY Design also worked and our SFP test using Transceiver toolkit was successful after this change.

Thanks and regards,

Ajay Mishra

[CheePin_C_Intel]

Hi Ajay,

Glad to hear that you have managed to resolve the issue and your design is up and running now. Thanks lot for the update.