Yes, you can disable JTAG access in Arria V using Design Security Features in Intel FPGAs. You can control various level of JTAG access control.
You may refer to the following document for more details:
Arria V handbook (page 319): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_5v2.pdf#page=...
I hope this will help.