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Ex. TRST = Disable , QuartusII Settings etc...
Target Device : 5AGXBA5D6F31C6N, 5AGXMA7G4F31I3N
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Hi KJalte2,
Yes, you can disable JTAG access in Arria V using Design Security Features in Intel FPGAs. You can control various level of JTAG access control.
You may refer to the following document for more details:
AN 556: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an556.pdf
Arria V handbook (page 319): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_5v2.pdf#page=319
I hope this will help.
Thanks😉

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