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I'm sorry, it's solved:
under ..\More Timing Settings\Ignore Clock Settings should be set to OFF !!- Mark as New
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The original post was using classic timing analyser that is no longer available.
You need to write an SDC file that defines all of the timings for the design- Mark as New
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Sorry i don't know how to write an SDC. is there any other way we could solve this... ? or could you please give me a small SDC eg. ?
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You need to write an SDC file to constrain your design. At a minimum it defines the clock, but also things like false paths, multicycle paths, IO delays etc.. Read this tutorial here:
https://www.altera.com/en_us/pdfs/literature/ug/ug_tq_tutorial.pdf
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