I have the following logic in my (VHDL) design:
-- Latch falling edge of read line when CS is active and then
-- keep DTR low until CS goes high again.
RD_and_CommCS <= RD_N OR COMM_CS_N; -- Use falling edge of ORed signals
-- to avoid condition where RD
-- arrives before CS.
DTR_Output : process (RD_and_CommCS, COMM_CS_N)
begin
if COMM_CS_N = '1' then
DTR <= '1';
elsif falling_edge(RD_and_CommCS) then
DTR <= '0';
end if;
end process;
RD_N and COMM_CS_N are inputs and RD_and_CommCS is an internal signal.
This logic works. It synthesizes a Flip Flop with COMM_CS_N going to the ACLR input and the output of the combinatorial logic (RD_and_CommCS) going to the negative edge CLK.
My question is how do I find out if it will always meet the required setup time from the ACLR input to the FF to the CLK input to the FF.
In other words, how can I guarantee that if RD_N is already low, the ACLR input will go inactive soon enough for the FF to see the negative going edge of RD_and_CommCS?
I have not been able to find this setup timing information in the Cyclone III documentation and I can't figure out how to create a constraint for this.
Thank you for your help.
