Auto Washing Machine for FPGA (VHDL Codes)

[Altera_Forum]

Hi guys,  

 i'm a new member for this website! nice to meet you all at here! I'm doing my degree of electronic course and looking for my final year project which named &nbspAuto Washing Machine for FPGA (VHDL Codes)!   i'm now headache for the shcematic diagram, truth tables, and VHDL source codes! Can someone help me to provide any imformation so that i can solve my project now! or someone give me some ideas to design this project !   actually i needing a flow to design the washing machince controller!   EXP: Design a 4 bits register the 4 bits register can form by 4 units of D flip flop!  so i just want to know to design a washing machine controller (CPU) by VHDL, should have what elements there? if i got the image about the flow then i can write the codes by myself! Be honest, my digital not strong also! Your help will be appreciated forever and ever!!  pLS help! urgently........

[Altera_Forum]

Try to have a look at www.opencores.org

[Altera_Forum]

no other ideas

[Altera_Forum]

I guess you are asking for some system design ideas. To be honest this is a very wide question!  

 I have no idea what functions your washing machine has (Apart from the obvious :) ) so cannot give advice on the function of the VHDL, State Machines etc  I imagine some kind of FPGA based embedded processor plus control software plus control logic is required.  Since this is an Altera Forum I suggest looking at the NIOS processor (Maybe get hold of a NIOS Eval kit). You can find the schematics on the Altera web but you will have to design your own interface logic within the FPGA to the washing machines working parts!  In a nut shell, think NIOS for processsors. Think about embedded software. Think about logic between the NIOS processor and washing machine and trawl around the Altera website.  Good luck

[Altera_Forum]

If you have a look at 

http://www.ncsu.edu/wcae/isca2006/submissions/benjamin.pdf there is a finite state machine model for a washing machine. You may take it as a starting point for your FPGA design. You need to convert this module into Verilog or VHDL language. Good luck!

[Altera_Forum]

is a simple CPU concept 

 it required , storage, ALU, FSM, and so on...  i have no idea to design since i fresh to this VHDL  I just want to show a basic output! it can be :  must have some counter to count timing, trigger motor to spin, LEDs, or seven segments display!  the vhdl program will download to Altera UP3 board (acts as FPGA) to do the all input output and wiring connections!  hopefully someone can give the guide now! i needing some information to do the proposal!

[Altera_Forum]

Do you need a good book to learn about Digital Circuit design with VHDL? I can suggest you one if needed, freely downloadable from the web.

[Altera_Forum]

--- Quote Start ---  Do you need a good book to learn about Digital Circuit design with VHDL? I can suggest you one if needed, freely downloadable from the web.  --- Quote End ---    post the url ... thx

[Altera_Forum]

The book is "Circuit Design with VHDL" by Volnei A. Pedroni, open your own account on www.scribd.com then search for it in its search engine and download it.

[Altera_Forum]

Download the web version of Quartus II and Modelsim of Alteras website. Get your vhdl book and start coding. A good tip is to read about modelsim testbenches and start testing your blocks with Modelsim (vhdl/verilog simulator). This is the best way to learn.  

 Quartus is filled with templates of code how to do state machines, registers, counters and so on. This may help if you get stuck.  //Ola

[Altera_Forum]

--- Quote Start ---  Download the web version of Quartus II and Modelsim of Alteras website. Get your vhdl book and start coding. A good tip is to read about modelsim testbenches and start testing your blocks with Modelsim (vhdl/verilog simulator). This is the best way to learn.   Quartus is filled with templates of code how to do state machines, registers, counters and so on. This may help if you get stuck.  //Ola  --- Quote End ---     ermmmmm i got the altera software! now i using it to simulate the waveform!  i just nid to sum1 provide a flow that a washing machine controller should have what elements if i want to design not too complex controller! like as FSM ( act as what function there) , want to design timer ( nid what logic function better) or any smiliar project theory!!??

[Altera_Forum]

I did not fully understand the question. I think you might have asked how to do a FSM and a counter/timer. I would advice you to read a vhdl book and do the exercises for the first few chapters to get the hang of the basic principles of parallell vhdl and processes. 

 If you want to do a fsm you use a process and a case statement. If you want to do a timer you'll need to create a counter (also a process). I myself program in VHDL by the way, if you're using verilog you can stop reading (:  If you create a new vhdl file in quartus you can right click in the editor and "insert template" and select a template for a whole file or code for different blocks.  //Ola

[Altera_Forum]

--- Quote Start ---  I did not fully understand the question. I think you might have asked how to do a FSM and a counter/timer. I would advice you to read a vhdl book and do the exercises for the first few chapters to get the hang of the basic principles of parallell vhdl and processes.  If you want to do a fsm you use a process and a case statement. If you want to do a timer you'll need to create a counter (also a process). I myself program in VHDL by the way, if you're using verilog you can stop reading (:  If you create a new vhdl file in quartus you can right click in the editor and "insert template" and select a template for a whole file or code for different blocks.  //Ola  --- Quote End ---     haha... i too crazy nw till i also dont know what i am talking about?!  actually i needing a flow to design the washing machince controller!   EXP: Design a 4 bits register the 4 bits register can form by 4 units of D flip flop!  so i just want to know to design a washing machine controller (CPU) by VHDL, should have what elements there? if i got the image about the flow then i can write the codes by myself! Be honest, my digital not strong also!