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Altera_Forum
Honored Contributor I
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Avalon Memory Mapped pipelined slave writes

I have been creating Avalon Memory Mapped master and slave interfaces for my custom components in my system. I have read through the Avalon specification multiple times, but I find one aspect of it confusing. 

 

In the section "3.5.4 Pipelined Transfers", it specifies that write transfers cannot be pipelined. 

 

However, the specification provides a writeresponsevalid signal which allows the slave to signal when a write response is valid on the response bus. (Which, by the way, writeresponsevalid is listed under the header "Pipeline Signals" in section "3.2 Avalon Memory-Mapped Interface Signal Roles".) The presence of the signal does not specifically imply that write transfers could be pipelined, but it would be possible using this signal in conjunction with the response bus. 

 

The thing that really confuses me is that there is an interface property called pendingWriteTransactions, which is "the maximum number of pending non-posted writes that a slave can accept or a master can issue". So, if a slave was not allowed to pipeline writes, how would the value of this property ever be anything but 1 (or 0, in the case that writeresponsevalid is not implemented)?
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Altera_Forum
Honored Contributor I
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The naming is kinda confusing I agree. Maybe some background will explain it better. Long ago Avalon only supported posted writes. The term pipeline reads refers to the fact that reads can have a separate command and data phase meaning something is buffering the read commands (Qsys fabric and/or the slave). Writes on the other have concurrent command a data phase because the data goes out with the write command, I think that's what the spec is referring to as it not being pipelined. This is not to say the write command and data is not pipelined by the Qsys fabric or the slave being accessed. 

 

With the addition of the write response signal now Avalon supports non-posted writes which allows your master to determine when the data is captured by the slave. Without the response it's not possible for a master to know when the write reached the slave but in both cases (posted and non-posted) there are typically at least 1 clock cycle between the write being send to the fabric and when the slave receives the write so the write data and command are typically pipelined through the fabric. 

 

I haven't used pendingWriteTransactions but from that description you include the write response port for your slave and the value you specify tells Qsys how many 2-bit responses it should expect to need to buffer on the way back to a master. Masters do not have the ability to signal if they are doing a posted vs non-posted write so if you include the response port the responses will always be buffered (and will be tossed away if the master doesn't support the response input).
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