AvalonMM plus UniPhy DDR3 Controller (without SOPC or Qsys)

[Altera_Forum]

Hello! 

I read all forum topics twice and didn't find any answer.  It whould be great if someone can help me!  Quartus 11.1; StratixIVGX dev.board;  At first I created ALTMEMPHY IP DDR3 (4 chips, each 16 data bits wide) and it is working very well at 333MHz. But Altera recommends to use UniPhy. Use UniPhy without SOPC or Qsys means to work with AvalonMM interface (The avl_beginbursttransfer signal I don't use because Altera doesn't recommend it. At first I tried with this signal and without - nevermind).   If open EMI tool you can see: https://www.alteraforum.com/forum/attachment.php?attachmentid=8772    https://www.alteraforum.com/forum/attachment.php?attachmentid=8771 You can see at write diagram after several writes waitrequest goes high and never goes back.  Read transactions is the same but after first avl_read.  local_init_done is OK, what may be a problem?  Thank you for help!!!

[Altera_Forum]

One more! 

 If the Controller Settings enable reordering option is turned OFF: https://www.alteraforum.com/forum/attachment.php?attachmentid=8773   Than read diagram is: https://www.alteraforum.com/forum/attachment.php?attachmentid=8774   It is very interesting diagram, burst count is only 2, but answers after one read request are more than 2 :) How is that may be?  Than write diagram is as the same (look like if reordering option is turned ON):  https://www.alteraforum.com/forum/attachment.php?attachmentid=8775   After some bursts the waitrequest goes high forever.

[Altera_Forum]

Now, I try to use the avl_beginbursttransfer signal according to Avalon spec... 

Results're more interested than before.  Read diagram:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8776   After two read requests wairequest goes high. After several tacts readdatavalid goes high forever.  Write diagram:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8777   You can see that burstbegin = avl_beginbursttransfer after several tacts goes high forever.  I couldn't find any mistakes in code...Could anybody help me? Thank you!

[Altera_Forum]

Every recompile IP UniPhy in Megawizard before project compilation you need to delete "_vector(0 downto 0)" from generated file...

[Altera_Forum]

hello, Antim_Klim, 

I use Quartus II 13.1 and Cyclone V. I meet this problem too, but I do not understand that you said "need to delete "_vector(0 downto 0)" from generated file...". Can you discribe it more clear, thank you.

[Altera_Forum]

Hello OmniKing, 

 I mean that if you recompile DDR3 IP it generates files. In which files the top file you need to open and delete all "_vector(0 downto 0)". In my configuration I have 4 chips in unbuffered dimm and IP generates for some signals not std_logic but std_logic_vector(0 downto 0). And if you run *.tcl for constraints you will have errors until you rename signals from std_logic_vector(0 downto 0) to std_logic. This mistake is allready talked in other forum threads.  It seems to me that all others work with DDR3 IP together with SOPC or Qsys. For my projects I don't need this systems, I never worked with them and I don't have time to learn them. Now I use altmemphy IP for DDR3, and it works well without any SOPC or Qsys. I created 4 (four) different DDR3 IPs without any problem. Althougth Altera sugessts to use UniPhy becouse it has some debug things. Yes, I saw that debug things allrigth work but IP don't work correctly. I tried in Quartus versions from 10.1 to 13, and in every versions IP doesn't work differently :). Probably I don't understand something and don't see my mistakes, but nobody answer me that it's true :).  GoodLuck, if you find out something, please write me!  Best wishes, Anton