Bare Metal Preloader / Register Documentation

[Altera_Forum]

Hello All: 

 I have been messing around a little bit with the Cyclone 5 SOC, and it is a really nice chip, which is why I want to stay with it. However, before I end up giving up on it, I thought I would ask in the forums about what I would like. Before I explain the situation, I want to make it clear that this is not an academic endeavor and that I am a professional software developer working for a company at the moment. I know exactly what I am getting in to as I have under taken such projects before.     I have a requirement to build a custom preloader, which means not using the built in routines that are generated from the Quartus II suite (Qsys). This is all fine and dandy until one figures out that it seems like this is impossible. I have been re reading document after document, and Altera makes it seem like it is possible to program the entire SDRAM controller from the HPS. After pulling up u-boot and numerous examples of how the SDRAM controller is initialized, the code uses undocumented registers (as far as I can see) for calibration and PHY setup. After looking at the register map for the HPS, the SDRAM controller starts at 0xFFC2(5000) and ends around 0xFFC250E0. The code in the SDRAM folder for the preloader makes usage of registers that start all the way from 0xFFC20000 and end somewhere around 0xFFC25170. There is something called a PHY manager, DATA manager, etc. in terms of the register blocks that are used.   Since these registers are not in the documentation, my first thought is that those registers were part of some custom FPGA fabric that mapped the registers into those memory ranges. This is not the case, because from the datasheet, the FPGA slave region that is in the middle of the HPS peripheral region starts at 0xFF200000 I believe and is only 2MB in size. These registers must be built in and undocumented.   I would like to be able to program the SDRAM controller myself and have no external dependency on things that have to be configured and downloaded. I want to look at the sequencer.c code file and know what the code is doing in regards to how it is setting up and modifying the registers. Not everybody wants to go through Qsys and Quartus to generate a piece of code for you. On top of that, I need very customized functionality in the preloader that is not offered by the pre canned stuff.   My specific question is this: Is the above possible? Can we program the SDRAM controller in a bare metal way without relying on Quartus to generate the code? I hope I am just not looking the right place to find the full register map for the controller. If this is the case, where can I find the register map? I can understand having to use Quartus to configure the interface between the FPGA and the HPS; however, I really hate having to rely on a code generator for my code.  Thanks

[Altera_Forum]

This version of SoC EDS is very nonfriendly, raw and green, through Doxygen :) 

I hope to see its good qualification of documentation for Baremetal developing approximately in Qua-15-16-17, only if we display many requests !.. Soon appears Q-14, may be small progress :) If not call bsp-editor or make that only once, after is possible edit sequencer.c for your requrements without risk lose your work, save it in other location... :) In any case, HPS contain embedded DDR-controller, its programming is not very differ in many variants, Altera may not show and describe all own "secret" registers. ...And you try to load our application from any flash except default SD-Linux ? It's base requirement for embedded programming, and not boot!

[Altera_Forum]

--- Quote Start ---  This version of SoC EDS is very nonfriendly, raw and green, through Doxygen :) I hope to see its good qualification of documentation for Baremetal developing approximately in Qua-15-16-17, only if we display many requests !.. Soon appears Q-14, may be small progress :) If not call bsp-editor or make that only once, after is possible edit sequencer.c for your requrements without risk lose your work, save it in other location... :) In any case, HPS contain embedded DDR-controller, its programming is not very differ in many variants, Altera may not show and describe all own "secret" registers. ...And you try to load our application from any flash except default SD-Linux ? It's base requirement for embedded programming, and not boot!  --- Quote End ---    I do not know what you mean linux is a requirement, because it's not. It is just that I cannot find the documentation to do bare metal like I want to. There is no reason why the preloader cannot load another application besides Linux when the chip boots.

[Altera_Forum]

Yes, need wait while Altera's processor department will be powerful. This is inevitable! 

FPGA is antagonist with ARM-proc (and any other procs), together difficulty.

[ieeeHuseyin]

Hello,

It's been a long time, does anyone have information about this matter?

Thanks.