Basic VHDL arithmetic not working on std_logic_vectors in Altera (vs Xilinx)

[EPrec]

I am porting code that works on a Xilinx FPGA to an Altera FPGA. In my code, I use basic arithmetic operations on std_logic_vectors. As an example, I define the following libraries in my VHDL file:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

Then if I define a signal:

signal my_signal : std_logic_vector(4 downto 0);

And then have a statement:

my_signal <= my_signal - 1;

On the FPGA, this statement seems to be impacting only bit 0 of my_signal instead of the entire vector. I've tried to rewrite the statement as:

my_signal <= std_logic_vector(unsigned(my_signal) - 1);

but that is throwing off errors when I try to build the project.

In Xilinx FPGA, the above statement works just fine, counting down the std_logic_vector (and turning over to 0b11111 when I subtract 1 from 0b00000). Why is this not working on the Intel/Altera FPGA?