Beginner device CPLD/FPGA selection for anti-aliasing filter

[Altera_Forum]

Hi all, 

 I am working on a HW design for power analysis of 8channel 50/60Hz signals that are sampled @ around 50kHz / channel. These signals needs to be filtered after sampling before transformation in frequency domain in a sharp anti-aliasing filter killing frequencies above 3kHz.  What performance level is required for such a task, i.e. how much oumph do I need to perform this kind of filtering? Can a CPLD do the job, or will a FPGA be required? (For now only the filtering needs to be done, transformation etc is done later by an MCU)  How do I even make an in-the-ball-park estimation of this?:confused:  Thankful for all thoughts/guesses.:D  /ThatIsTheQuestion

[Altera_Forum]

I entered your filter requirements into MATLAB's FDAtool and with the settings shown in the GUI you need about 50 coefficients. 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=8659   Since you are sampling at 50kHz, and your FPGA/CPLD can run at least at 50MHz to 100MHz, you have at least 1000 FPGA clocks per ADC clock. This means that your filter can easily be implemented using a single multiplier and some RAM. CPLDs do not have these types of resources, so a small FPGA would be more appropriate. A CPLD could probably do it too, but FPGAs are nicer to deal with when doing signal processing, as you have RAM and can use the SignalTap II logic analyzer.    --- Quote Start ---   For now only the filtering needs to be done, transformation etc is done later by an MCU   --- Quote End ---   What transformation?   If you are only interested in the 50/60Hz signal, then there is a transform called the Goertzel algorithm  http://en.wikipedia.org/wiki/goertzel_algorithm  that can be used essentially as the FFT but of just one channel.  Cheers, Dave

[Altera_Forum]

Hi Dave, and many thanks for a quick answer! 

 With transformation I mean going from time to frequency domain to be able to perform harmonic analysis etc. This could of course be done in the FPGA as well, but with current solution it is done later in a separate MCU.  Could you explain shortly what you mean by a single multiplier?  Unfortunately the filter you simulated seems to drop too much on frequencies below 3kHz. I guess that creating a filter which passes signals <3kHz and blocks signals >3kHz is only possible in theory, but something closer to that is required since I need to measure correctly up to the 50th harmonic (60Hz*50 = 3kHz...)  So how is that achieved? A higher order?  (As you notice, I am new to this...)  Best Regards / ShakeTheSpear

[Altera_Forum]

An economic implementation would e.g. use a 4:1 CIC decimator and a higher order FIR filter for the last decimation stage. In any case, there's a tradeoff between filter transition steepness and required filter complexity. 

 Did you notice that audio ADCs respectively codecs have nearly perfect anti-aliasing filters and decimation down to an intended sampling rate, partly even programmable.

[Altera_Forum]

Hey FvM, 

  --- Quote Start ---  An economic implementation would e.g. use a 4:1 CIC decimator and a higher order FIR filter for the last decimation stage. In any case, there's a tradeoff between filter transition steepness and required filter complexity.   --- Quote End ---   I haven't had to implement FIRs at such low frequency. Once you get to having a serial filter, the FIR becomes a RAM with coefficients and a multiplier, or a MACC circuit. Given that 1k-samples of coefficients will fit in an FPGA RAM block easily enough, would you bother adding the complexity of a CIC followed by cleanup FIR? Seems like more trouble than its worth ...    --- Quote Start ---   Did you notice that audio ADCs respectively codecs have nearly perfect anti-aliasing filters and decimation down to an intended sampling rate, partly even programmable.  --- Quote End ---    This could be a better solution than using an ADC+FPGA+uC; find an ADC that already includes the digital signal processing you need and interface that to the micro.  FvM - Do any particular codec part numbers come to mind?  Cheers, Dave

[Altera_Forum]

CIC usage would primarly reduce complexity, that's why it's classically used for multi-rate filters of oversampling ADCs. But I agree that a serial FIR won't consume much resources besides block RAM. In so far it's a straightforward solution, even with quite large number of coefficients if you can afford the RAM capacity.  

 The WM8731 codec untilized on many Terasic boards can be used with 8 kHz standard sampling rate, or any rate of your choice by adapting the clock frequency.

[Altera_Forum]

Dear Dave and FvM. 

 Thank you for all your feedback! This is a new board and I am only at investigation stage trying to identify rough BOM cost for different solutions, which is not easy when I do not have the knowledge required.  The MCU does not have available performance to do this filtering, so I am trying to compare adding another MCU or a FPGA for the job (or other smarter solutions if any)  I will look into the audio ADC suggestion, I fear though it will be a bit costly due to the 8 channels.  Many Thanks! /Will_I_Am

[Altera_Forum]

Stereo audio ADCs like PCM1808 are quite cheap.

[Altera_Forum]

--- Quote Start ---  Stereo audio ADCs like PCM1808 are quite cheap.  --- Quote End ---    Thanks, I will look in to it. Clearly interesting!

[Altera_Forum]

Maybe this thread is moving off-topic, but can someone explain to me why an ADC (PCM1808) with 24-bit resolution have a gain error of typ3% max6%? 

Of course this could probably be fixed in design with calibration, but it seems a bit high with respect to the number of bits. I also do not find any information regarding gain accuracy vs temperature in the datasheet :-/ http://www.ti.com/lit/gpn/pcm1808

[Altera_Forum]

IMHO it's not the only problem with those kind of converters. I'd really like to know what's the point of using 24 bits when you have a 99dB SNR. Can't you achieve the same results with a 18 bit converter and use a random generator for the low 6 bits? You spare some money and complexity, and still make the marketing guys happy.