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Behaviour of MAX10 PLL output during reset, PFD disable and lock-loss

Honored Contributor II

As the title suggests I am interested in the behaviour of the PLL output clock of the Altera/Intel MAX10 during the following edge cases: 


  • reset (areset = '1')  

  • phase-frequency-detector disable (pfdena = '0')  

  • lock-loss (areset = '0', pfdena = '1', locked = '0')  



The simulation model generated by the Quartus MegaWizard simply outputs 'X' immediately (reset and PFD dsiable) or after some clock cycles (lock-loss).  


However, at least when the PFD is disabled, the sparse documentation suggests that the output clock should continue toggling with the last locked frequency while slowly drifting away towards lower frequencies. Moreover, since the documentation explcitly states that the PLL output clocks have no enable, my understanding is that the output clock is in fact toggling all the time, except when the PLL (and its output counter) is held in reset. 


Can someone comment on this or possibly check this out on some development board? (my board is still in shipment...)
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