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Altera_Forum
Honored Contributor I
760 Views

Bi-direction signal issues

Hi Guys, 

 

I met an issue for Bi-direction signals. When the state is for output from FPGA, the data is not correct... Please help me. 

 

So I have a top module and connect the inouts to a submodule, and the value assignment is in the submodule. Will this be an issue? 

 

Here is part of the code: 

 

entity top is 

port( 

clk : in std_logic;  

nRst : in std_logic;  

 

emif_cs_n : in std_logic; 

emif_R_nW : in std_logic; 

emif_addr : inout std_logic_vector(9 downto 0); 

emif_data : inout std_logic_vector(7 downto 0) 

 );  

end top; 

 

 

architecture behavior of top is 

 

 

component sub is  

port( 

nRst : in std_logic;  

clk : in std_logic;  

 

 

emif_cs_n : in std_logic; 

emif_R_nW : in std_logic; 

emif_addr : inout std_logic_vector(9 downto 0); 

emif_data : inout std_logic_vector(7 downto 0) 

 );  

end top; 

 

 

sub_u: sub  

port map( 

nRst => nRst , 

clk_100M => clk_100M , 

 

 

emif_cs_n => emif_cs_n , 

emif_R_nW => emif_R_nW , 

emif_addr => emif_addr , 

emif_data => emif_data ,  

); 

 

 

end behavior; 

------------------ 

entity sub is  

port( 

nRst : in std_logic;  

clk_100M : in std_logic;  

--emif  

emif_cs_n : in std_logic; 

emif_R_nW : in std_logic; 

emif_addr : inout std_logic_vector(9 downto 0); 

emif_data : inout std_logic_vector(7 downto 0) 

 );  

end sub; 

 

emif_data <= rdata_reg when (rd_period = '1') else (others => 'Z'); 

emif_addr <= raddr_reg when (emif_cs_n = '0' and emif_R_nW = '1') else (others => 'Z'); 

---------------- 

here is from signaltap 

https://alteraforum.com/forum/attachment.php?attachmentid=15595&stc=1  

 

So what causes the bi-direction signals not following the register value?
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
48 Views

You dont show what rd_period or emif_cs_n and emif_R_nW. If these are setting the bus to 'Z', then you will be reading the values coming from off chip.

Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

You dont show what rd_period or emif_cs_n and emif_R_nW. If these are setting the bus to 'Z', then you will be reading the values coming from off chip. 

--- Quote End ---  

 

 

Hi, they were always in "emif_cs_n = '0' and emif_R_nW = '1'" contition... That's why I think it's weird..
Altera_Forum
Honored Contributor I
48 Views

OK the issue is solved. The problem is: the other side is also sending data to FPGA during the period, so both sides are sending data, there is conflict~~

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