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Valued Contributor III
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Bidirectional, tri-state buffer, VHDL problem

I m working with tg68k mc68k core emulation for FPGA. When i compile code i get 31 ADRESS BUSS pins, also 16 input, and 16 output pins. I need to join those 16 in and out pins to get 16 bidirectional pins for DATA BUS. I write some VHDL but i have some problems. Code generates 16 bidirectional pins as i wanted but also there are 16 input and 16 output pins, and no ADDRESS BUSS pins. As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins to join them in 16 bidirectional pins using tri-state buffer.  

 

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY data_bus IS PORT( data_bus : inout STD_LOGIC_VECTOR (15 downto 0); oe : IN STD_LOGIC; input : IN STD_LOGIC_VECTOR (15 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)); END data_bus; ARCHITECTURE signals OF data_bus IS signal data_in : STD_LOGIC_VECTOR (15 downto 0); signal data_out : STD_LOGIC_VECTOR (15 downto 0); signal data_oe : STD_LOGIC; BEGIN PROCESS(oe) BEGIN IF oe = '1' THEN data_bus <= data_out; ELSE data_bus <= "ZZZZZZZZZZZZZZZZ"; data_in <= data_bus; END IF; END PROCESS; END signals;
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Valued Contributor III
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You would want to tristate data_bus rather than data_out  

data_bus <= "ZZZZZZZZZZZZZZZZ";
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Valued Contributor III
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Oh i put old code sorry i did that hour ago but i have this problem i described in first post. What is wrong with my code. I updated code i m using now.

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Valued Contributor III
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Give this a try: 

 

Remove the whole process, and replace it with the following: 

 

data_in <= data_bus; data_bus <= data_out when oe='1' else (others => 'Z');  

 

This the way I usually describe tristateable signals. 

 

Good luck! 

 

 

 

Ben
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Valued Contributor III
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I found where is the problem ( i think). All is working fine but other missing signals that i need (ADRESS BUSS etc...) are in TG68.vhd file. Also in that file i can see every signal that i used in my code. As i m thinking i need somehow to connect TG68.vhd to my code and reuse signals from that file.

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Valued Contributor III
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I solved this problem, but now i have one more. How ti integrate sdram controller to tg68 core ? Do you have any ideas, is there any examples to do this.

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