Binary to Binary coded deicmal help

Altera_Forum · ‎04-30-2011

Hi guys,

I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input.

However, it seems like the binary goes through unchanged! Which I assume means +3 never happens... But why? Any ideas?

Thanks in advance, the code I've got so far is below.

module bcd(binary, bcd);
    input binary;
    output bcd;
    
    wire w0,w1,w2,w3;
    assign w0 = binary;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    add3 (.in(w2<<1), .out(w3));
    assign bcd = w3;
endmodule

module add3( in, out);
    input in;
    output out;
    reg out;
    
    always@(in)
    begin
        out = in;
        if(in>4) out = out + 3;
        if(in>4) out = out + 3;
    end
endmodule

Altera_Forum · ‎04-30-2011

Just a wild gues. Your design is without clock (asynchronous) and could be running into logic hazards.

Altera_Forum · ‎04-30-2011

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Just a wild gues. Your design is without clock (asynchronous) and could be running into logic hazards.

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I tried adding a clock to the sensitivity list in "add3". That didn't help, or did I do it wrong?

Altera_Forum · ‎04-30-2011

if you just insert clock only in add3:

always @ (posedge clock)

...

than that should register the signal assignments and should be ok to make your design synchronous. The clock must be available as input if you are testing actual hardware.

Altera_Forum · ‎04-30-2011

Don't know where you get the algorithm, but it seems not to do what it should. Check with pencil and paper! Perhaps you can give a numerical example of what you want to achieve.

There should be no principle problem to implement the algorithm completely asynchronously.

Altera_Forum · ‎04-30-2011

Thanks for the speedy replies!

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if you just insert clock only in add3:

always @ (posedge clock)

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I tried using CLOCK_50 which I think should work on my DE1? And the display just read 0

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Check with pencil and paper! Perhaps you can give a numerical example of what you want to achieve.

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Thats what is driving me absolutely crazy. I have done it hundreds of times on pen and paper and it's work.

I'm trying to convert binary like 01011 to 0001 0001.

Here's a run through.

TENS|ONES|01011

0000|0010|11 SHIFT 3 (no +3)

0000|0101|1 SHIFT 4 (ones is >4 so +3)

0000|1000|1

0001|0001| SHIFT 5

And the 5th shift gives you the BCD!

Altera_Forum · ‎04-30-2011

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There should be no principle problem to implement the algorithm completely asynchronously.

--- Quote End ---

Certainly clock is not needed "in principle" just for this piece of work and especially for a beginner using finger buttons to generate inputs. But for a safer design methodology within a project and working on faster inputs I will use the clock.

moreover, the statement:

out = out + 3 implies feedback and I believe it can't survive asynchronously

Altera_Forum · ‎04-30-2011

I am a bit unsure about the feedback statements out = out + 3 ...etc.

why not try: out = in + 3 if it is equivalent

Altera_Forum · ‎04-30-2011

Thanks I tried that earlier and have just double checked. The result is the same.

Altera_Forum · ‎04-30-2011

You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.

Even if you clock the out registers, the feedback will keep adding 3 if condition is true.

Altera_Forum · ‎04-30-2011

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You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.

Even if you clock the out registers, the feedback will keep adding 3 if condition is true.

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But each time it adds +3 it would have just reset out to in? Because of the block assignments? I'm fairly sure that's not happening for some reason. I tried removing the condition and +3 is happening. So either the condition is never true? Which I can't make sense of or the if clause is messing up the timming?

I tried using modelsim but it's complaining about my not having a license :/

Altera_Forum · ‎04-30-2011

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out = out + 3 implies feedback

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No it doesn't. It's a simple sequential expression.

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I have done it hundreds of times on pen and paper and it's work.

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I checked one example (dec 22 / hex 16, should give hex 22), and it was wrong.

Altera_Forum · ‎04-30-2011

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I checked one example (dec 22 / hex 16, should give hex 22), and it was wrong.

--- Quote End ---

TENS|ONES|22

0000|0000|10110

0000|0101|10 (third shift) ones>4 so +3

0000|1000|10 (fourth shift)

0001|0001| (shift 5)

0010|0010|

It works. I didn't invent double dabble.

Altera_Forum · ‎04-30-2011

Just noticed you are adding 3 to ones yet the code adds 3 to all in bits.

Shouldn't you say:

if in(8:5) > 4 out(8:5) = out(8:5)+3; as the tens

Altera_Forum · ‎05-01-2011

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Just noticed you are adding 3 to ones yet the code adds 3 to all in bits.

Shouldn't you say:

if in(8:5) > 4 out(8:5) = out(8:5)+3; as the tens

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Oh my, I can;t believe I didn't spot that in two days! It's working much better now. Still not working great but I can work on that in the morning. Thanks so much!

Update:

I removed the final add3 now it works perfectly.

Here's the final code in working order.

module bcd(in, out);
    input in;
    output out;
    
    wire w0,w1,w2,w3;
    assign w0 = in;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    assign w3 = w2 << 1;
    assign out = w3;
endmodule

module add3(in, out);
    input in;
    output out;
    reg out;
    
    always@(*)
    begin
        out = in;
        if(in>4) out = in + 3;
        if(in>4) out = in + 3;
    end
endmodule