Block Memory Pipeline Controls

[waxwing]

Have an old design in a Cyclone V, and recently added a 2-port, single-clock block memory; the read side is used to stuff words into an Avalon-mm interface.  So to accommodate wait states, and overcome the read latency of the memory (two clocks, one for input address, one for output data), I implemented both the rd_addressstall and rden pipeline controls.  But, the rden seems to have no effect at all on the behavior of the read data port.  I worked around it by omitting the dead data register from the block memory macro and simply adding a register external to the read data port, enabled by the same signal that was driving rden.

That works as intended and all is well; but I am curious about the intention of the rden control.  How should it work?

Thanks.

[RichardTanSY_Intel]

You may checkout this user guide on how the rden signal works.

https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/read-enable.html

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/embedded-memory-modes.html

Regards,

Richard Tan

[RichardTanSY_Intel]

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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Richard Tan