block ram refers to those prewired asic-like rams available to logic fabric through ports and configrable by user. they are of various graininess.distributed ram makes use of (some) LUTs of logic fabric as memory instead of implementing them for logic. these are good for multiple small blocks(fine grain). e.g. 3 input LUT can provides 8 1 bit locations.
Thanks Kaz,I am using cyclone iv EP4CE55F23I8LN, so where i get the information about how much block ram & distributed ram it has ? Also, how can i use this information ?
the Cyclone IV family doesn't have distributed RAM. it has one type of block RAM, M9K. you'll find the number of RAM blocks in the Overview link and details about the M9K in the Memory linkCyclone IV Overview http://www.altera.com/literature/hb/cyclone-iv/cyiv-51001.pdf Cyclone IV Memory http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf
Thanks thepancake,As kaz reply "distributed ram makes use of (some) luts of logic fabric as memory instead of implementing them for logic. these are good for multiple small blocks(fine grain). e.g. 3 input lut can provides 8 1 bit locations." 1) So how can u says that Cyclone IV family does not have distributed RAM ? 2) Is there any Cyclone FPGA which has Distributed RAM , also how to configure LUT as distributd RAM ? 3) so Whenever an FPGA is configured , is it actually program this block RAM only ?
The "Distributed" Ram is a Xilinx terminology, The Altera terminology doesn't call it this, but it can do something similar, in that they can use the registers in the LE's as ram cells. But this eats (In both Xilinx and Altera fabrics)One distinguisher between the families in the Altera world is the sizes of the block rams available: Personally I liked the way the Stratix II family is structured best, small 512 bit blocks, (Great for fifos and small rams. M4K rams, Good size for larger delay rams, etc, and large M-Rams (512 K Bits) fast cpu storage and/or large tables.. Lately, the have gone to a single larger sized ram. And although the are flexible in how you use them, it doesn't fit my designs very well. We have one design that fits in a 2S30 device, but we are forced to use a 3C55 device because of the ram structures of the Cyclone 3 family. And it's getting worse, In both Xilinx and Altera families. Pete
--- Quote Start --- The "Distributed" Ram is a Xilinx terminology, The Altera terminology doesn't call it this, but it can do something similar, in that they can use the registers in the LE's as ram cells. But this eats (In both Xilinx and Altera fabrics) --- Quote End --- Xilinx's distributed RAM feature uses each LE as a 16x1 or 32x1 bit RAM. With Altera, you only get 1 bit per LE. Pyushim, a) Altera FPGAs don't have a "distributed RAM" feaure like Xilinx do. b) no c) FPGA configuration is stored on dedicated RAM cells, which are not available for use as part of the design.