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Valued Contributor III
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Booting a bare metal application from QSPI flash

Hi, 

 

I'm developing a bare metal application on the Arrow SOCkit demo board. I want the HPS to boot the application from QSPI flash. Everything works fine when I'm using the debugger, but when i program the image to the QSPI flash and reset the board, nothing happens. 

 

At the moment I'm not even sure if my preloader executes correctly from QSPI. Is there any way to verify that the preloader is running? 

 

-The preloader was built with 'boot from qspi' enabled 

-I programmed he preloader image into the QSPI flash 

-The application image was also programmed into QSPI flash at the correct offset. 

-The BOOTSEL jumpers are set to '111', which should configure the device to boot from QSPI. 

 

Did I leave anything out? Any ideas on what I can measure or observe on the outside to see what is going on in the chip?
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Valued Contributor III
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Please, in details write all operations before power off/on of kit. 

I also don`t may start from QSPI or write new Preloader to SD-card. 

Remake Preloader, fill it to 0 address 4nd with quartus_hps, application (Altera BareMetal example for 4 diodes mighting GNU) fill to 60000 -- don`t boot on power on. 

In DS-5 debugger runs a copy of Preloader, it inited DDR, loads my application from QSPI to DDR at 02000000, check CRC succsessful, I through "file hello.axf" loads debug-info for application, steps in debugger, and in _initio() hang! 

My application with HPS-jumpers 28-30 in pos right-left-left from manuals also is not started in DS-5! And with default left-right-left successful started.
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Valued Contributor III
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I solved it,  

 

When I made the application image I set the entry point to 0x0 when it should have been 0x2000000. The mkimage example in Altera's getting started guide has the entry point set at 0 and I just copied that.
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Valued Contributor III
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Not work! 

 

In http://www.rocketboards.org/foswiki/documentation/preloaderubootcustomization I read: 

 

--- Quote Start ---  

HPS Boot Flow The typical HPS boot flow includes the following stages: 1. BootROM. 2. Preloader. 3. U-Boot. 4. Linux. 

The BootROM and the Preloader stages are needed for all the applications in which the Cyclone V or Arria V SoCs are used. 

The U-Boot and Linux are used by the GSRD, but they are not required for all applications. 

The next stage boot image loaded and executed by the Preloader does not necessarily needs to be an U-boot image. For example the Preloader can: 

* Load bare-metal applications directly, 

* Load RTOS-es or OS-es directly, 

* Load another bootloader that can subsequently load the applications. 

The only requirement is that the next stage image has the proper mkimage header, that is required for U-boot to recognize the image. 

--- Quote End ---  

 

I download cv_soc_devkit_ghrd.tar.gz from http://releases.rocketboards.org/release/2013.11/gsrd/ghrd, unzip it to T:\Wit\DS-5\gsrd\cv_soc_devkit_ghrd\, make all "GSRD - Generating and Compiling the Preloader" (http://www.rocketboards.org/foswiki/documentation/gsrdpreloader), only on Windows 7 and with check option BOOT_FROM_QSPI instead BOOT_FROM_SDMMC or BOOT_FROM_RAM, address QSPI_NEXT_BOOT_IMAGE default set to 0x60000. 

After generate and compile all preloaders with call "make" in folder T:/Wit/DS-5/gsrd/cv_soc_devkit_ghrd/software/spl_bsp, result is in preloader-mkpimage.bin ("Preloader image with the BootROM required header"), need to fill in QSPI flash. 

I set jumpers to boot from QSPI as http://www.rocketboards.org/foswiki/documentation/gsrdqspiprogram

J28 right shorted J29 left shorted J30 left shorted 

and rePowrer board. 

 

Intuitively add to Makefile from standard blinking project Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU imported to DS-5 from  

C:\altera\13.1\embedded\examples\software\Altera-SoCFPGA-HardwareLib-16550-CV-GNU.tar.gz in making target "$(ELF):" 2 lines: 

./objcopy --gap-fill=0xff -O binary hwlib.axf hwlib.bin ./mkimage -A arm -O u-boot -T standalone -C none -a 0x02000000 -e 0x02000000 -n "baremetal image" -d hwlib.bin T:/Wit/DS-5/gsrd/cv_soc_devkit_ghrd/software/spl_bsp/hwlib.img.bin 

to add embedded functionality, fast making binary flash-image from output file hwlib.axf and put result in preloader output folder. It is right in all options ? This may contain errors of flow comprehension. 

 

Near preloader-mkpimage.bin in folder T:/Wit/DS-5/gsrd/cv_soc_devkit_ghrd/software/spl_bsp I create file 2qspi.sh with: 

quartus_hps -c 1 -o PV -a 0 preloader-mkpimage.bin quartus_hps -c 1 -o PV -a 0x60000 hwlib.img.bin 

and run it on SoC EDS console with kit, waits 12 min, rePower -- only U-Boot-spl is started: 

U-Boot SPL 2013.01.01 (May 16 2014 - 11:19:27) BOARD : Altera SOCFPGA Cyclone V Board SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SF: Read data capture delay calibrated to 3 (0 - 7) SF: Detected N25Q512 with page size 65536, total: 67108864 

and after hang, no diodes are blinked. 

 

Then I run this filled version U-Boot-spl (T:/Wit/DS-5/gsrd/cv_soc_devkit_ghrd/software/spl_bsp/uboot-socfpga/spl/u-boot-spl) direct in DS-5 with debug features after load to hi memory, breakpoint on jump_to_image_no_args(), next image was loaded from 60000 in flash, its CRC checked succsessful. 

 

Then I load it debug info with "file T:\Wit\DS-5\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU\hwlib.axf" through Command window, steps and see call to exception vector 02 on 4th command SVC: 

S:0x02000040 : B __cs3_start_asm_sim ; 0x200018C -> S:0x0200018C : ADR r1,{pc}+0x44 ; 0x20001d0 S:0x02000190 : MOV r0,#0x16 S:0x02000194 : SVC # 0x123456 

It is trap to hivecs area: 

S:0xFFFF0008 : LDR pc, ; = 0xFFFF0024 

, and forever cycled in hi address space FFFF0000. This is "Supervisor Call". Him permissible here, on 4th asm-command of application? 

 

Where I bad ? Is too many possible variants in chain to introduce errors. I even don`t know, "J28 right shorted" signify 0 or 1 in BOOTSEL tables ;) 

 

More than -- my application hwlib.axf hang DS-5 download on try debug it direct execution for these jumpers "J29-right, J29-left, J30-left" ! :) 

 

I ask Altera expand ug_soc_eds.pdf in next version of EDS with detail process of preloadering and filling my BareMetal application to flash for succsessful starting, not through Linux, or make one button for all longest chain in DS-5, theirs reaction is undefined :( 

 

Check my chain, please, or display its in details !
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Valued Contributor III
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I demand include to next Quartus version separate simple sections in ug_soc_eds.pdf for work with Baremetal application, fully described, not  

casually and thin hint. 

And to SoC EDS please add folders with precompiled preloaders for all described/proposed variants of flash boot, checked in Altera/Rocketboard in practice.
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Valued Contributor III
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hey witfred  

 

did you solve this ? cause I am stuck on this problem too. 

however I bypassed the __cs3_start_asm_sim by using the original armulator linker script. but still it doesnt work
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Valued Contributor III
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Yes, I solve, in http://electronix.ru/forum/index.php?showtopic=121400 recipe in home language. Big application based on hwlib load self from QSPI to DDR, download .rbf to FPGA and through 2 sec blink with its LEDS! 

About armulator and __cs3_start_asm_sim don't know, problem was in ARM-semihosting in hwlib and Preloader: hwlib before main() uses system call "SVC 123456" with various input parameters (open stdin/stdout etc.), debugger hooks these calls and send to host, receive results and pass back to application. 

Without debugger or after command "set semihosting enabled false" call "SVC 123456" enter exception 2 instead processing in debugger, go to standard pure vector FFFF0008 and cycle there forever. 

I read semihosting API on ARM site, research necessary calls and answers back, add my semihost-simulating function "int svc_my_handler(int R0, int R1)" to C:\altera\13.1\embedded\examples\hardware\cv_soc_devkit_ghrd\software\spl_bsp\uboot-socfpga\common\s... and set her address to FFFF0008 from "__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)", disable interrupts (in my kit very often strange 1 to pin CP15.I) and all work !!! 

May be in application without using hwlib all is OK and as usual, if not using semihosting and open stdin + stdout. 

In 14th version of SoC EDS appear these possibility or wait another 15+th ? :)
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Valued Contributor III
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have you try eds ver14.0? 

 

i have experienced same issues.
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Valued Contributor III
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You might find the QSPI baremetal examples here to be useful: http://www.altera.com/support/examples/soc/soc.html

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Valued Contributor III
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Baremetal examples is good, however booting is only from SD in last :) 

When moderator pass my post with recipe booting from QSPI ?!! :) 

14th version I download, install near 13.1 -- it deletes DS-5 from 13.1, install new DS-5, keeps links to debug configuration DB to 13.1 directoryes for old debuggable projects in my workspace, all not work -- its badly. 

Unlikely get QSPI-boot in 14.0 -- this is secret :)
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Valued Contributor III
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5 days ago I reply to arkadish123 and see page as in first attachment moder.jpg. 

I save my text to recipe.txt (2nd attachment) and upload it now -- what if moderator is on leave? :) 

 

...I download GPIO example from BO-link-page and don`t run in EDS 13.1 -- this Makefile uses toolchain arm-altera-eabi-*, what is appears in EDS 14.0, and after edit Makefile to use arm-none-eabi-* request new linker script: 

ld.exe: cannot open linker script file cycloneV-dk-ram-hosted.ld: No such file or directory 

If I find these file in C:\altera\14.0\embedded\host_tools\mentor\gnu\arm\baremetal\arm-altera-eabi\lib\ and copy to project folder, then another error: 

cycloneV-dk-ram-hosted.ld:262: undefined symbol `__cs3_reset_cycloneV_dk_ram' referenced in expression collect2: ld returned 1 exit status 

In short, in 13.* these examples not compatible, in all redme.txt-s writed "Note: This example was developed with and tested against SoC EDS 14.0b199.".
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Beginner
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Hello,

I have a custom board with cyclone V SOC . I have a 1Gbit QSPI flash attached to the HPS portion of SOC. I want to boot the HPS with qspi flash. I able to do it debug mode. But not able to do it in program mode. what i mean is that i am able to load the rbf files into the qspi flash and read back this files and program the fpga successfully in debug mode. But when i try to do it program mode it is not working. I have generated preloader_-mkpimage.bin file with all the necesssary settings as mentioned in HPS qspi boot guide documentation. i load this preloader-mkpimage in 0x00000000 address of QSPI flash using the commands in SOC Command shell. then i load my application bin file generated after compilation of my design at 0x60000 address of flash by using commands in SOC EDS Command shell. Both this operation is successfull. MSEL pins are correctly selected for QSPI Boot. When i reboot the equipment the system is not booting. Am i missing certain settings at bsp generation or in make file or the linker file. Please specify.

 

 

Regards

Avi

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Beginner
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Hello,

I have a custom board with cyclone V SOC . I have a 1Gbit QSPI flash attached to the HPS portion of SOC. I want to boot the HPS with qspi flash. I able to do it debug mode. But not able to do it in program mode. what i mean is that i am able to load the rbf files into the qspi flash and read back this files and program the fpga successfully in debug mode. But when i try to do it program mode it is not working. I have generated preloader_-mkpimage.bin file with all the necesssary settings as mentioned in HPS qspi boot guide documentation. i load this preloader-mkpimage in 0x00000000 address of QSPI flash using the commands in SOC Command shell. then i load my application bin file generated after compilation of my design at 0x60000 address of flash by using commands in SOC EDS Command shell. Both this operation is successfull. MSEL pins are correctly selected for QSPI Boot. When i reboot the equipment the system is not booting. Am i missing certain settings at bsp generation or in make file or the linker file. Please specify.

 

 

Regards

Avi

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Beginner
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We made our own baremetal tutorial.
this tutorial explains the start to end complete procedure for making the baremetal application on the HPS.

overview about this tutorial

  1. you need to make the DDR3 settings in the QSYS HPS.
  2. you need to use the “hps_isw_handoff” generated by QSYS HPS and make the preloader from bsp editor.
  3. do the settings of the bsp editor so that you can boot from QSPI.
  4. make the preloader and store the preloader on the QSPI.
  5. make the binary image of your baremetal application using the fromelf command in DS-5 Build steps.
  6. add the baremetal header to your binary file which is generated from your c code compilation.
  7. program this binary file on the QSPI and power off and on your device.
 

 

now you are successful to boot your c program

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