Burst mode of DDR SDRAM

[Altera_Forum]

Dear all, 

 I am not very understanding burst mode, we all know DDR SDRAM has burst length of 2 or 4 or 8. Does it mean the transfer data length should be times of 2 or 4 or 8?  What is the units of burst length?   For example, if I have 16 bytes, transfer in a burst length of 2, do I need to issue 8 command read/writes?   What if my data size is odd? does it mean either I need to repack the data to times of burst length? or tranfer most of the data in burst mode, the remaning data in non-burst mode?  Thank you very much!

[Altera_Forum]

--- Quote Start ---  Dear all,  I am not very understanding burst mode, we all know DDR SDRAM has burst length of 2 or 4 or 8. Does it mean the transfer data length should be times of 2 or 4 or 8?   --- Quote End ---   For SDR - yes. And you can use full page mode.     --- Quote Start ---   What is the units of burst length?    --- Quote End ---  Word. If you use 8 bit SDRAM you burst 8 mean 8 bytes. If you use 4 bit wide burst 8 give you 4 byte.     --- Quote Start ---   For example, if I have 16 bytes, transfer in a burst length of 2, do I need to issue 8 command read/writes?    --- Quote End ---  Yes. And you may no need change page.     --- Quote Start ---   What if my data size is odd? does it mean either I need to repack the data to times of burst length? or tranfer most of the data in burst mode, the remaning data in non-burst mode?   --- Quote End ---  You can use mask pin in DRAM. It's 8 bit wide pin. En example if you need to write 8 bit data to 32 bit DRAM. You need to mask 3 byes and unmask one byte.

[Altera_Forum]

hey i dont think any of the ddr's support the full page mode.burst lengths of 2 / 4 are the only ones supported by the ddr.this increases to 8 in the ddr3. i think atrem_bond may have answered regarding the sdram memory by mistake. 

the burst length will determing the number of consecutive read/write operations the ddr will perform to get the corresponding amount of data read/written. for e.g. with a burst length of 4 and a read operation with a data width on the dram size of 8, the dram will start performing a read operation from the starting address given to the next 4 '8'bit locations and will output 8-8-8-8 bits of data in all to the user. the column address will increment internally as long as the row doesnt reach the end. also,since it is ddr, the 4 read transactions will take a total of 2 clock cycles on the memory side. and you dont have to give 4 read transactions for the same. only 1 read transaction with a burst length of 4 has to be selected for the above operation and so forth. take care kk