C10GX programmed via MT25QU256ABA8E12-0SIT

[MSmit6]

I have a new version of a board that has been in use for a few years. The changes between this board and the previous revision is minimal and had little if anything to do with the Cyclone 10. The only changes around the FPGA is the LVDS clock for memory was changed from 50 MHZ (1.8V) to 100 MHz (3.3V). The clock connected to the Clkusr pin is still 100MHz (2.5V). The second change was the addition of an additional UART.

What we are seeing on this rev of the board is a very slow startup. The time ranges from a couple of seconds to several minutes. We finally tracked it down to the interface between the FPGA and the MT25QU256ABA8E12-0SIT. This is the same part we have been using for some time along with the MT25QU256ABA8E12-0AAT when the standard part is unavailable. The circuit for this is exactly as shown in the C10GX Handbook for a single EPCQ-L device.

At power up we immediately see nSTATUS AND nCONFIG go high. The nCSO0 signal and the DCLK do not go active for a long period of time (seconds to minutes). We have never seen anything like this. We also don't see anywhere in the Handbook that allows for access to these signals. The programming is set in Quartus to use the 100MHz Clkusr clock. From the handbook it looks as though that actual clock used is 60 MHz. When we see DCLK eventually go active we do see 60 MHz.

Does anyone have any ideas what could be causing this delay?

The design does include a NIOS Core that the previous revision did not have.

[NurAiman_M_Intel]

Hi,

Apologize for the delay in response.

Can you provide us configuration signal/waveform? eg: nSTATUS, etc..

Regards,

Aiman

[MSmit6]

Aiman,

The timing looks exactly like Figure 144 in section 7.3.4.2 AS Configuration Timing of the Cyclone 10 GX Handbook except the DCLK never begins transitioning. The nCSO signal will transition every 7-10 ms presumably trying to restart the programming.

As I was probing the DLCK pin a couple of days ago I saw a burst of clocks and the FPGA started running. Previously I had a wire on the DCLK to be able to monitor it on the scope. I repeated the probing of the DCLK 20 times and every time there was a burst of clock pulses and the FPGA would program and begin running. I added a 33 pF capacitor to the DLCK line and now the FPGA programs every time.

I have no idea why putting a cap on the clock would suddenly make the circuit begin to work. I have 4 boards with virtually identical circuits between the C10 GX and the MT25Q device. This is the only one that has ever shown this behavior. The same thing happen on all 15 prototypes that we had built.

Do you have any idea why a cap would matter here?

[NurAiman_M_Intel]

Hi,

Further checking with my team, it might because power is not sufficient enough to program. It is a normal practice to add capacitor for the FPGA to program in this case.

Regards,

Aiman

[NurAiman_M_Intel]

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