C4gx dev kit and TSE

[Altera_Forum]

Hello all,  

 I work on C4GX dev board, I use the board update portal design exemple and I use Simple Socket server on my NIOS application.  First I've worked with the subscription version (30 days evaluation). I worked only on the SSS application with NIOS II SBT tools.  My application works fine.  Now my trial have expired and I use a web lisence.  I have problems when I make modifications in the nios with QSYS. For exemple I only rename PIO_LED in PIO_LED_Test.  I generate it, go in quartus and compile. I refresh my workspace in SBT, generate BSp, clean, build and debug.  When I run my program in debug it stop at "INFO : PHY[0.0] - Auto-Negotiation PASSED" see it in nios II console.  But i can pass this step in "step by step" debugging but it always stop at:   /* Wait for the descriptor (chain) to complete */  while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(dev->base) &  ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) );  see it in altera_avalon_sgdma.c  I don't know what happened. I'am lost.  I need help.  Thanks.

[Altera_Forum]

Are you using the system id component to check that the hardware and software images are made for the exact same system? It's just an idea, but Quartus could have switched to an opencore evaluation mode when you changed the license. In that case it creates the image in a sof file whose name ends with _time_limited.sof instead of the regular .sof file. You could still be using the old file with a new software image, but the Nios programmer would spot this if you have a system id component. 

Another thing to look at is timing. Is the design properly constrained and does it meet timing requirements? If it doesn't, even a slight change could cause the entire system to fail.

[Altera_Forum]

Hi,  

 Thanks for the reply and for your ideas. I use system id and I verify it, it's OK. I'am programming with the time_limited.sof.  I think like you that It could be a timing problem.  Maybe I don't add a .sdc in my quartus but when I check I have the tse_mac_constraints.sdc.  I made a test, I copy the altera original project and I copy it. I compile it with quartus to create the time_limited.sof.  I program it and run my own SSS application in NiOS. And It works.  But If I made any change in my nios (add PIO or rename...) after I can't run my application it always fail at at "INFO : PHY[0.0] - Auto-Negotiation PASSED".  thanks.

[Altera_Forum]

Do you have a top level .sdc that gives at least the frequencies of your clock inputs, and the derive pll instruction? 

In the timequest report you can have a look at the clocks list and check if your clocks are listed there, with the correct frequencies. Check also during compile that you don't have a "does not meet timing requirements" critical warning.

[Altera_Forum]

hi Daixiwen,  

 Thanks for your interest. I found something interesting but I can't explain.  I use the board update portal for the dev kit (made with Quartus v10 by altera).  But I use Quartus v11. When I Update my NIOS with SOPC builder everything is OK. And when I use Qsys it's not working.  Nonetheless in my quartus workspace I added the good .sopc files (from sopc or from qsys) but it is doesn't working when I use Qsys.  I don't know why if I use Qsys it doesn't work.  thanks bye

[Altera_Forum]

Hi, 

 Perhaps the problem is that the TSE constraints created by QSys are incorrect by default.   If you look into the file YOUR_SYS\synthesis\submodules\YOUR_SYS_tse_mac_constraints.sdc (where YOUR_SYS is the name of your QSys system) you'll see a section "# Customer modifiable constraints" in the beginning of the file, where you're supposed to fill your board's clock names and values.   And if I remember correctly, even the Altera's own examples don't use those pin names and you must change the TSE constraint file before the Ethernet becomes more reliable.   The main problem is that the QSys generates the constraint file every time you generate the QSys system and thus overwrites any changes you've made into that constraint file! Not very user-friendly ...   I've created the following TCL-script (I've named it fix_qsys.tcl) to modify the contraints to match my system's pin names:    package require fileutil proc processContentsOfTseMac {fileContents} { # map search replace return } # Fix TSE MAC constraints fileutil::updateInPlace nios_sys/synthesis/submodules/nios_sys_tse_mac_constraints.sdc processContentsOfTseMac    If you add the following line into your project's .qsf file, the Quartus will run the script every time it compiles and thus fix the QSys generated constrains:    set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:fix_qsys.tcl"    Hope this helps, Jari

[Altera_Forum]

thanks for your help,  

 But If I compare the .sdc files from altera folder and the .sdc from my project, they are the same.  I downloaded and install the board_update_portal project exemple made with quartus v11 on altera web site.  When I recompile the project without any changement It works. The I rename PIO_LED into PIO_LED_TEST and It doesn't work.  Then If re-rename into PIO_LED it doesn't work too.  I think I will continue using SOPC builder.  thanks.  Someone know I can use on-chip memory insted of ssram ??