CDR reference clock

[Shubhall]

In the case of 10G base R  design, while configuring the native phy which clock to give for rx_cdr_refclk0. In my case I am taking refclk from the another bank using the non-bonded xN clocking(because of this only serial clk ~5GhZ from 1E bank is coming from xN lines and given to local clock generation block of the channel 5 in 1C transceiver bank). I am also not sure if it is necessary to give this rx_cdr_refclk0 as input. In my phy intantiation file .... it is coming as input pot. Kindly help. 

I am using Arria 10 soc device (10AS066N3F40E2SG)

Rev C 

[ZiYing_Intel]

Hi Shubhall,

Thanks for submitting the issue.

Please do let me have some time to investigate on it and I will be get back to you with findings.

Best regards,

Zi Ying

[Shubhall]

okay ... also, please let me know if any info required from my side.

Thanks

Shubhangi

[ZiYing_Intel]

Hi Shubhangi,

May I know the devkit name that you are using?

Best regards,

Zi Ying

[Shubhall]

Hi Zi Ying,

I am using Intel® Arria® 10 SX SoC Development Kit (https://www.intel.in/content/www/in/en/products/details/fpga/development-kits/arria/10-sx.html).

Thank you

Shubhangi

[ZiYing_Intel · Accepted solution]

Hi Shubhangi,

It's required to be used if your design require the reference clock input to the RX clock data recovery.

For your information, clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

To perform the optimum performance of GT channel, the reference clock is recommended to be from a dedicated reference clock pin in the same bank. For details information about the input reference clock, you may refer to link below, Section 3.2, pg383, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/input-reference-clock-sources.html

For further information about non-bonded configuration, you may refer to link below, Section 3.11, pg411, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/non-bonded-configurations.html

Best regards,

Zi Ying

[ZiYing_Intel]

Hi Shubhangi,

Since the case has been idling without further inquiries, I would like to close this case.

If you still have any inquiries after the case closed, please do feel free to submit another issue.

Best regards,

Zi Ying

[Shubhall]

okay ..