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CPLD Max V equivalent gates

Neha
Beginner
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Hello, 

 

I am checking for an alternate to replace EPM3064A. I see the actual gates are mentioned as 1250. I dont see this "actual gates" count given in Max 5 OR Max2 series CPLD. Instead we have Logic Elements. I am trying to figure out what number of equivalent Logic Elements should I select that fulfills the requirement of 1250 actual gates. 

 

Best Regards

NEHA

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Neha
Beginner
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Please do help me in understanding this difference on LEs and equivalent gates and their equivalence. Also please suggest a part number from these families that can be used for redesign meeting the number of I/Os and Functions

 

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AminT_Intel
Employee
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Hello Neha,

 

You can refer to our FPGA catalog for our device selections: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/sg/product-catalog.pdf .

 

I am sorry I am not clear with your questions. Can you re-phrase it?

 

Thanks.

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Neha
Beginner
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Neha_0-1624276961497.png

Per the above sanp from MAX3000 specification sheet I see that there are 1250 usable gates. I am trying to figure out an equivalent CPLD that can replace Max 3000 part. 

 

Neha_1-1624277081384.png

In Max 5 series if i see, then I have the basic unit as LE(logic elements). Should I take 1270 LEs part 5M1270Z to replace  EPM3064A(1250 actual gates), comparing actual gates value with LEs? 

Is LEs and actual gates value of these two different spec sheets comparable for selection of alternative in CPLD?

 

 

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AminT_Intel
Employee
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Hello,

 

Yes they are similar things.

 

Thanks.

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MBenca
New Contributor I
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Hello Neha,
I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elements
A fragment from the mentioned article:
"Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates."

I would recommend to try to implement your project in the Quartus design system for Intel/Altera MAX V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite). According to my experiences with CPLD devices it is more important to have enough flip-flops. But it depends on the current project of course.

Regards,
Martin

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AminT_Intel
Employee
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We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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